With complexities of Systems-on-Chip rising almost daily, the system designers have been searching for new methodology that can handle given complexities with increased productivity and decreased times-to-market. The obvious solution that comes to mind is increasing the level of abstraction. However, the most important things that system designers care about are system architectures (components topology), HW/SW performance, and the communication protocols. System designer has to make decisions on these factors in a very short time. Furthermore, the transaction level model (TLM) can satisfy the requests on simulation speed and the information that system designer need.
We implement a TLM virtual prototype platform with SystemC composing with the variable wrappers. The basic modules: ISS interface, user-define modules and a flexible bus. Based on the infrastructures, a much faster modeling process of the system can be achieved in this thesis. Finally, the platform will run the whole-system-simulation to verify the functional model and collect the dynamic information on the buses and IPs to diagnose the bottle-neck of the system.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0817105-230520 |
| Date | 17 August 2005 |
| Creators | Liu, Jin-lin |
| Contributors | Jer-Min Jou, Ing-Jer Huang, Shiann-Rong Kuang, Pei-Yin Chen, Ko-Chi Kuo |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | English |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0817105-230520 |
| Rights | unrestricted, Copyright information available at source archive |
Page generated in 0.0023 seconds