Delta-sigma data converters have gained popularity in both analog-to-digital and digital-to-analog converters (ADCs and DACs) due to their simplicity, high linearity and immunity to many analog circuit imperfections. These data converters include features such as oversampling, noise-shaping, and (historically) single-bit quantization. Single-bit converters are preferred for their inherent linearity. This is a feature which multibit converters cannot realize due to the unavoidable phenomenon of element mismatch. Because of this problem, multibit converters have been largely unexplored, and the market has seen few multibit commercial products.
Earlier work has shown that multibit DACs constructed with unit elements can be applied in an architecture which shapes the spectrum of the noise caused by element mismatch. The basis of this thesis is the experimental verification of such a DAC. A Xilinx 4005 FPGA is utilized to implement a 3rd-order 4-bit delta-sigma modulator and the mismatch-shaping logic, while a custom IC consisting of 16 individually-controlled differential current sources implements the unit-element DAC. The final DAC achives a Spurious Free Dynamic Range (SFDR) of 96 dB at a sampling rate of 62.5 kHz. / Graduation date: 1997
| Identifer | oai:union.ndltd.org:ORGSU/oai:ir.library.oregonstate.edu:1957/33999 |
| Date | 09 May 1997 |
| Creators | Hudson, William Forrest, 1971- |
| Contributors | Schreier, Richard |
| Source Sets | Oregon State University |
| Language | en_US |
| Detected Language | English |
| Type | Thesis/Dissertation |
Page generated in 0.0025 seconds