Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2005. / In RF power transistor characterisation, the designer is confronted with low impedance
measurements (typically from 1 Ohm to 12 Ohm). These transistors are contained in
metal-ceramic packages of which the lead widths vary with power capability. This thesis
presents a high-quality fixture design with low impedance TRL calibration standards for
characterisation of an LDMOS transistor. Pre-matching networks are used to transform
to the low impedance environment. Since these pre-matching networks are independent
of the termination impedance, the low impedance port can always be designed to comply
with the same dimension as the device which is being measured.
| Identifer | oai:union.ndltd.org:netd.ac.za/oai:union.ndltd.org:sun/oai:scholar.sun.ac.za:10019.1/2510 |
| Date | 12 1900 |
| Creators | Malan, Pieter Jacob De Villiers |
| Contributors | Van Niekerk, C., Van der Walt, P. W., University of Stellenbosch. Faculty of Engineering. Dept. of Electrical and Electronic Engineering. |
| Publisher | Stellenbosch : University of Stellenbosch |
| Source Sets | South African National ETD Portal |
| Detected Language | English |
| Type | Thesis |
| Format | 3717353 bytes, application/pdf |
| Rights | University of Stellenbosch |
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