In this thesis we propose to realize the performance benefits of applicationspecific hardware optimizations in a general-purpose, multi-user system environment
using a dynamically extensible microprocessor architecture. We have called our
dynamically extensible microprocessor design the Extensible Microprocessor without
Interlocked Pipeline Stages, or eMIPS.
The eMIPS architecture uses the interaction of fixed and configurable logic
available in modern Field Programmable Gate Array (FPGA). This interaction is used to
address the limitations of current microprocessor architectures based solely on
Application Specific Integrated Circuits (ASIC). These limitations include inflexibility,
size, and application specific performance optimization. The eMIPS system allows
multiple secure extensions to load dynamically and to plug into the stages of a pipelined
central processing unit (CPU) data path, thereby extending the core instruction set of the
microprocessor. Extensions can also be used to realize on-chip peripherals, and if area
permits, even multiple cores. Extension instructions reduce dramatically the execution
time of frequently executed instruction patterns. These new functionalities we have developed can be exploited by patching the binaries of existing applications, without any
changes to the compilers.
A FPGA based workstation prototype and a flexible simulation system
implementating this design demonstrates speedups of 2x-3x on a set of applications that
include video games, real-time programs and the SPEC2000 integer benchmarks. eMIPS
is the first realized workstation based entirely on a dynamically extensible
microprocessor that is safe for general purpose, multi-user applications. By exposing the
individual stages of the data path, eMIPS allows optimizations not previously possible.
This includes permitting safe and coherent accesses to memory from within an extension,
optimizing multi-branched blocks, and throwing precise and restart able exceptions from
within an extension.
This work describes a simplified implementation of an extensible microprocessor
architecture based on the Microprocessor without Interlocked Pipeline Stages (MIPS)
Reduced Instruction Set Computer (RISC) architecture. The concepts and methods
contained within this thesis may be applied to other similar architectures. Given this
simplified prototype we look forward to propose how this architecture will be expanded
as it matures.
| Identifer | oai:union.ndltd.org:tamu.edu/oai:repository.tamu.edu:1969.1/5976 |
| Date | 17 September 2007 |
| Creators | Pittman, Richard Neil |
| Contributors | Liu, Jyh-Charn |
| Publisher | Texas A&M University |
| Source Sets | Texas A and M University |
| Language | en_US |
| Detected Language | English |
| Type | Electronic Thesis, text |
| Format | 1420088 bytes, electronic, application/pdf, born digital |
Page generated in 0.0027 seconds