博士 / 國立交通大學 / 電子研究所 / 98 / Continually scaling down the CMOS technologies into nanoscale generation imposes significant challenges in integrated circuit (IC) reliability, where electrostatic discharge (ESD) protection has become one of the major concerns. To meet such reliability specifications are necessary for IC product qualification. From the perspective of ESD, the similar gate oxide breakdown voltage and trigger voltage of MOSFET devices increased the design difficulty. Moreover, the secondary device characteristics of MOSFET have been considered in nanoscale CMOS generations. The most important impact for ESD is the gate direct tunneling current, which happens between the gate and silicon beneath the gate oxide, occurs while MOSFET implementing in a nanoscale CMOS process. Such gate tunneling current could induce a substantial fraction of overall leakage current in a chip. The traditional ESD protection circuit with a large gate oxide dimension suffers serious gate leakage issue. The on-chip ESD protection circuit in nanoscale CMOS process should be design with consideration of gate tunneling current to achieve a low standby leakage current during the normal circuit operation condition. During the ESD stress, the on-chip ESD protection circuit should provide efficient protection capability to assure the safety of the internal circuit which has a small gate oxide breakdown voltage in nanoscale CMOS process. For the mixed-voltage I/O interfaces with thin gate-oxide devices, the on-chip ESD protection designs will meet design difficulties, such as gate-oxide reliability constraints and undesired leakage current paths. In high-voltage Bipolar-CMOS-DMOS (BCD) technology, high-voltage transistors have been widely used for display driver ICs, power supplies, and power management ICs. The high-trigger-voltage and low-holding-voltage characteristics of HV transistor have been found to cause latchup or latchup-like failure and insufficient ESD efficiency. Therefore, how to develop an efficient on-chip ESD protection design is an important challenge for high-voltage IC products. In this dissertation, the ESD design constraints in nanoscale CMOS process, mixed-voltage I/O interfaces, and high-voltage CDMOS technology are presented. Furthermore, the novel design solutions for on-chip ESD protection circuit have been developed to meet the design constraints in such technologies and applications. To provide effective on-chip ESD protection with low standby leakage current in nanoscale CMOS technology, a new power-rail ESD clamp circuit by using the silicon controlled rectifier (SCR) device and ESD detection circuit with substrate-triggered technique is proposed. The SCR device without poly-gate structure has good immunity against the gate leakage current. The special ESD detection circuit is designed with consideration of gate current to reduce the standby leakage current. The new proposed design has been fabricated and verified in a 65nm fully-silicided CMOS process. The new proposed power-rail ESD clamp circuit can achieve 7kV in human-body-model (HBM) and 325V in machine-model (MM) ESD levels while consuming only a standby leakage current of 96nA at room temperature under 1-V bias. In order to protect the mixed-voltage I/O interfaces in nanoscale CMOS technology, a new high-voltage-tolerant ESD clamp circuit is proposed to protect the mixed-voltage I/O circuits for receiving signals with 2?eVDD voltage level. The devices used in the high-voltage-tolerant ESD protection design are all low-voltage thin gate-oxide devices. The gate current of each thin gate devices in the high-voltage-tolerant ESD detection circuit has also been considered. By using the ESD protection scheme with the ESD bus and the proposed high-voltage-tolerant ESD clamp circuit, the mixed-voltage I/O circuit can be well protected. The new proposed circuit has been fabricated in a 1-V 65-nm CMOS process for experimental verification. In high integrated electronic system, the mixed-voltage I/O design with NMOS blocking technique is applied for receiving 3×VDD, 4×VDD, and even 5×VDD input signals without the gate-oxide reliability issue. In this dissertation, two new ESD protection design by using only 1×VDD low-voltage devices for mixed-voltage I/O buffer with 3×VDD input tolerance are proposed. Two different special high-voltage-tolerant ESD detection circuits are designed with substrate-triggered technique to improve ESD protection efficiency of ESD clamp device. These two ESD detection circuits with different design concepts both have effective driving capability to trigger the ESD clamp device on. These ESD protection designs have been successfully verified in two different 130nm 1.2-V CMOS processes to provide excellent on-chip ESD protection for 1.2-V/3.3-V mixed-voltage I/O buffers. In high voltage CDMOS technology, the high-voltage DMOS is widely used as on-chip ESD protection devices. The trigger voltage of the high-voltage devices is too high to protect the output buffer. Such characteristics will cause the high-voltage DMOS susceptible to the latchup or ESD danger in the practical applications. To greatly improve ESD performance of the high-voltage DMOS devices, gate-driven and substrate-triggered circuit techniques are applied. The proposed gate-driven and substrate-triggered ESD protection circuits have been successfully verified in a 0.35-?慆 5V/40V bipolar CMOS DMOS (BCD) process. In addition, the power-rail ESD protection design can be also achieved with stacked structure to protect 40-V power pins without latchup issue in the smart power ICs. In this dissertation, the novel ESD protection circuits have been developed for nanoscale CMOS process, mixed-voltage I/O interfaces and high-voltage BCD process with high ESD robustness. Each of the ESD protection circuits has been successfully verified in the testchips. The proposed ESD protection circuits in this dissertation can achieve the benefits of low standby leakage current, high ESD performance, and latchup-free characteristics for whole chip ESD design in CMOS ICs.

博士 / 國立交通大學 / 電子物理系所 / 98 / In the past two decades, terahertz photonics and applications have progressed remarkably. However, tunable components in terahertz range are relatively underdeveloped. The present tunable terahertz devices, however, have limited range of tunability and have to be operated at cryogenic temperatures far below room temperature. To conquer the drawbacks, various tunable terahertz devices operated at room temperature based on nematic liquid crystal have been demonstrated in our group. In this work, based on the experience of fabricating the nematic liquid-crystal-based tunable devices, we demonstrated several tunable devices with grating structure to manipulate THz waves. We constructed a Kerr-lens mode-locking Ti:sappire laser with maximum power 450 mW, 90 MHz repetition rate, and 64 fs in pulse width. A conventional photoconductive antenna based THz-TDS was constructed that can characterize the broadband terahertz signal in the range, 0.1 - 4.0 THz. To investigate the terahertz beam steering, an improved THz-TDS with movable detecting part was constructed with an optical fiber. The improved THz-TDS can characterize the terahertz signal below 1.0 THz. It can detect the terahertz pulse directly and can be more convenient and lower cost than that using the liquid-helium-cooled Si bolometer. We choose the fused silica and nematic liquid crystal E7 and MDA-00-3461 to fabricate our devices. The materials for tunable devices design should have the properties of large birefringence and small absorption. The complex refractive indices of these materials were characterized by the conventional THz-TDS at room temperature 24.5?aC. In the THz range, 0.2-2.0 THz, the complex refractive indices of fused silica are n=1.95, k < 0.01. The ordinary and extraordinary indices of E7 are no = 1.58, ne = 1.71, ?菣o=0.03, and ?菣e=0.01, and which of MDA-00-3461 are no = 1.54, ne = 1.72, ko=0.03, and ?菣e=0.01, respectively. In this frequency range, these materials do not show any sharp resonant absorption and clear dispersion. The studies of the optical constants of NLC E7 and MDA-00-3461 in terahertz range show the attractive potential of the applications due to the comparable large birefringence and relative small extinction coefficient. In this work, we demonstrated several liquid-crystal-based tunable devices with grating structure. These devices including magnetically and electrically controlled phase gratings, and the electrically phase shifter array. We designed the phase gratings that can be utilized as tunable beam splitters, and the phase shift array can be utilized as a beam steerer.

博士 / 國立交通大學 / 電子物理系所 / 98 / The large third-order nonlinearities of Nd:YVO4 and Nd:GdVO4 are employed to realize the compact efficient self-mode-locking in the range of several GHz in solid-state lasers with a simple linear cavity. With a pump power of 2.5 W, the lasers produce greater than 0.7 W with the pulse width in the picosecond region at the operating wavelength of 1064 nm. Furthermore, we also have demonstrated the self-mode-locked Nd:YVO4 laser at 1342 nm. The average output power was up to 1.2 W at an incident pump power of 10.2 W. The pulse width was experimentally found to be less than 12ps. In order to improve the stability of self-mode-locked lasers, we have demonstrate the control of Nd:YVO4 laser. The experimental results reveal that reducing the number of longitudinal lasing modes can diminish the fluctuation to effectively improve the pulse stability. Considering the spatial hole burning (SHB) effect, an analytical expression is derived to accurately estimate the maximum number of longitudinal lasing for a practical design guideline. Therefore, the stable self-mode-locked laser can induce a novel method to measure the refractive indexes and thermal optical coefficient of certain crystals. The experimental results are in good agreement with the results in texts. Besides the fundamental mode self-mode-locked lasers, we have reported the self-mode- locked Hermite-Gaussian Nd:YVO4 lasers with an off-axis pumping scheme. With a pump power of 2.2 W, the average output power for 3.5 GHz mode-locked HG modes vary in the range of 350-780 mW for the TEM0,m modes from to . We also use simple astigmatic mode converters (AMC) to convert the mode-locked HG TEM0,m beams in to Laguerre-Gaussian (LG) modes for generating picosecond optical vortex pulses. Furthermore, the modulated pulse trains are observed as there are two adjacent transverse modes coupling. The modulated frequencies can apply to determination of thermal lens in mode-locked lasers.

博士 / 國立交通大學 / 電信工程研究所 / 98 / In this dissertation, the design methodologies and implementations of RF receiver circuits for multiband and ultra-wideband communication applications are proposed. There are four parts in this thesis, including: (1) the design of two triple-band low-noise amplifiers (LNAs) using switched resonators and a noise cancelation technique, (2) the design of dual-band image rejection mixer, (3) the analysis and design of three low-power UWB LNAs, and (4) the design of voltage-controlled oscillator (VCO) with phase-noise improvement. First of all, the design of two triple-band LNAs with switched resonators is presented and fabricated in the TSMC 0.18-μm CMOS process. The proposed triple-band LNAs are demonstrated the feasibility to effectively decrease the size of multi-band RF systems by using a switched component. In addition, a considerable noise power diminution in MOS devices with an additional larger substrate resistor is presented in the second approach of the triple-band LNA. A 32% noise reduction of MOS devices can be achieved at 2.5 GHz without extra chip area, CMOS process steps and dc power. This noise reduction technique in MOS device is very promising in the nowadays LNA designs. Secondly, this thesis presents a 2.45/5.2 GHz dual-band Gilbert downconversion mixer with image rejection function is presented, which is implemented in the 0.18-μm CMOS technology. The proposed differential dual-band image rejection circuitry is employed for the 2.45/5.2 GHz WLAN application to effectively diminish the dc power consumption and complexity of circuit design compared to the traditional Hartley or Weaver architectures. Moreover, the cross-connected pair consisted of NMOS and PMOS transistors in the proposed notch filter will further ameliorate the image rejection capability. The IC prototype attains conversion gain of 10.5/11 dB, IIP3 of -4.9/-5.2 dBm for RF= 2.45/5.2 GHz and IF=500 MHz while the image rejection ratio is better than 36/45 dB in the whole operation bandwidth. Thirdly, three low-power UWB LNAs using 0.18-μm CMOS technology are presented. Due to the FCC’s stringent power-emission limitation at the transmitter, the received signal power in the UWB system is smaller than those of the close narrow-band interferers such as the IEEE 802.11 a/b/g WLAN, and the 1.8 GHz DCS/ GSM. Therefore, we proposed a wideband input network with out-band rejection capability to suppress the out-band interference for our first UWB LNA. Moreover, a feedback structure and dual-band notch filter with low power active inductors will further attenuate the outband interferers without deteriorating the input matching bandwidth in the second UWB LNA. The 55/48/45 dB maximum rejections at 1.8/2.4/5.2 GHz, 15 dB power gain, and 3.5 dB minimum noise figure can be measured while consuming dc power of only 5 mW. On the other hand, to further improve the noise figure performance of the above out-band rejection LNAs, a new matching technique is presented in the third UWB LNA. The proposed broad-band input match network can be obtained easily by selecting an appropriate width of the transistor, which could effectively avoid the usage of the low-Q on-chip inductors in the input network. The IC prototype achieves good performances: 16.2 dB maximum power gain, better than 10 dB input return loss, and 2.3 dB minimum noise figure while consuming dc power of only 6.8 mW. Finally, a low-power 5.25 GHz VCO with phase-noise improvement is designed in a 0.18-μm CMOS 1P6M process. Due to the usage of a larger value of parallel capacitor, an additional harmonic-suppressed capacitor, and an appropriate bulk bias voltage of the transistor, a good figure of merit (FOM) of -190 dBc/Hz can be achieved without extra chip area and CMOS process steps. The fabricated VCO operates from 5.12 to 5.36 GHz with a power consumption of 1.9 mW and active chip area of 0.15 mm2. The measured phase noise at 1 MHz offset is about -119 dBc/Hz.

碩士 / 國立交通大學 / 電信工程研究所 / 98 / A power management system can ensure system to operate within specification and achieve nominal power dissipation through power/speed modulation. For example, Intel Pentium M processor has speedstep technology which has six frequency/voltage modes to switching. For such power management system, we need a programmable clock generator to provide various operation frequencies. In this thesis, a glitch-free DLL-based clock generator using a feedback switching detector is proposed for a programmable power management system. The proposed circuitry utilizes feedback switching detector to eliminate undesired glitch problem which is generated by switching feedback stage of DLL. The output frequency range is from 100MHz to 1.6GHz with 8 steps for operation frequency. The power consumption is 37.8mW and P-P jitter is 23.316ps at 1.6GHz. After measurement we fix the problem found in measurement and revise edge combiner. The revise extends output frequency range to 1.8GHz. The improvements make this work more suitable for a power management system.

碩士 / 國立交通大學 / 電信工程研究所 / 98 / Without using any pilot and training symbols, a serially concatenated turbo transceiver is proposed for joint channel estimation, symbol detection and LDPC decoding in Rayleigh fading channels. In fading channels, the dependence of variable nodes in the factor graph lingers slightly according to the fading speeds. However the independence assumption is necessary for the cycle-free condition of LDPC codes. Hence we added the design criterion that the variable nodes connected to the same check node are restricted to be in different coherence intervals to meet the constraint. The performance of finite-length LDPC codes would be affected both by the number of coherence intervals and the fading speed.

博士 / 國立交通大學 / 電控工程研究所 / 98 / Signal quality of data transmission is significantly affected by clock jitter of Phase-Locked Loops (PLLs). However, production test for clock jitters is too expensive to implement. Built-In Self-Test (BIST) for clock jitter measurement becomes an alternative solution for production test. Basically, BIST methodologies are based on Time-to-Digital Converters (TDCs) which convert phase differences of a tested clock and a reference clock into low-speed digital signals for test equipments to measure. In this thesis, we proposed three kinds of TDCs and BIST circuits for different applications. The first one is designed for measuring clock jitter of charge-pump PLLs. The BIST is based on a novel high resolution TDC. Small area overhead is achieved by reusing the Voltage-Controlled Oscillator (VCO) and loop filter of the tested PLL as part of the TDC. The experiment result shows that the resolution is about one pico-second and the measurement error is smaller than 20%. The second BIST circuit is proposed for measuring timing jitter of Spread-Spectrum Clocks (SSCs). The BIST circuit can separate low-frequency phase drifting caused by frequency modulation and high-frequency jitter. Because of lack of dedicated instruments for SSC timing jitter measurement, a jitter estimation method is also developed for validating the feasibility of the BIST circuit. A 1.2GHz 10-phase Spread-Spectrum Clock Generator with a jitter measurement circuit is designed and fabricated. The experimental results show that the proposed built-in measurement approach has an error of less than 0.0026UI. The third BIST circuit is developed for testing the relative timing jitter of data and clock recovery circuits. This BIST circuit doesn’t need a high resolution delay line to achieve high accuracy measurement result, but uses calibration and curve-fitting algorithms. Calibration is done by switching the VCO of the tested PLL into free-running mode and using statistical theories to acquire accurate delay time of the delay buffers in the TDC. This BIST circuit also separates deterministic jitter and random jitter by adopting the bathtub curve-fitting algorithm and estimates total jitter at bit-error rate=10-12 level.

碩士 / 國立交通大學 / 管理學院碩士在職專班管理科學組 / 98 / The usage of LED is becoming wide spread with more creative applications. This survey explores which factors underlie the LED component purchasing decision. These insights provide LED manufacturers a means to improve services to better meet customer needs. The research also explores the relationship between LED package types and LED applications, the result provides a better understanding for LED users to select components for industrial and commercial applications.

博士 / 國立交通大學 / 機械工程學系 / 98 / This dissertation aims to examine numerically heat and mass transport phenomena in the plate methanol steam micro-reformer (including methanol steam micro-reformer and methanol catalytic combustor). The first focus is to investigate the effects of geometric and thermo-fluid parameters on the methanol conversion and gas concentration distributions of the methanol steam micro-reformer in order to obtain better channel designs and operating conditions. Furthermore, a methanol steam micro-reformer with a methanol catalytic combustor is considered in the present work. The results can provide comprehensive information for designing the plate methanol steam micro-reformer. This study can be divided into two parts. In the first part, the research only considered the plate methanol steam micro-reformer, namely the methanol catalytic combustor is not included in it. Firstly, a 2-dimensional channel model of the methanol steam micro-reformer is established to investigate effects of geometric and thermo-fluid parameters on performance and heat and mass transfer phenomena in micro-reformer channels. The results of the modeling suggest that the methanol conversion could be improved by 49 %-points by increasing the wall temperature from 200 ℃ to 260 ℃. The results also show that the CO concentration would be reduced from 1.72% to 0.95% with the H2O/CH3OH molar ratio values ranging from 1.0 to 1.6. The values of parameters that enhance the performance of micro-reformer were identified, such as longer channel length, smaller channel height, thicker catalyst layer, larger catalyst porosity, lower Reynolds number and higher wall temperature. Secondly, a 3-dimensional channel model of the methanol steam micro-reformer is developed to investigate the effects of various height and width ratios and channel geometric size on the reactant gas transport characteristics and micro-reformer performance. The predictions show that conduction through the wall plays a significant effect on the temperature distribution and must be considered in the modeling. The predicted results also demonstrated that better performance is noted for a micro-reformer with lower aspect-ratio channel. This is due to the larger the chemical reaction surface area for a lower aspect-ratio channel. The results indicate that the smaller channel size experiences a better methanol conversion. This is due to the fact that a smaller channel has a much more uniform temperature distribution, which in turn, fuel utilization efficiency is improved for a smaller channel reformer. Finally, the established 3-dimensional channel model of a plate methanol steam micro-reformer extends to be a plate methanol steam micro-reformer with serpentine flow field. A numerical investigation of the transport phenomena and performance of a plate methanol steam micro-reformer with serpentine flow field as a function of wall temperature, fuel ratio and Reynolds number are presented. The methanol conversion is improved by decreasing the Reynolds number or increasing the S/C molar ratio. When the serpentine flow field of the channel is heated either through top plate (Y=1) or the bottom plate (Y=0), we observe a higher degree of methanol conversion for the case with top plate heating. This is due to the stronger chemical reaction for the case with top plate heating. In the second part, a numerical study is performed to examine the characteristics of heat and mass transfer and the performance of a plate methanol steam micro-reformer with a methanol catalytic combustor. Firstly, a three-dimensional channel numerical model of a micro-reformer with combustor is developed to examine the effects of various flow configurations and geometric parameters on micro-reformer performance. Comparing the co- and counter-current flows via numerical simulation, the results show that the methanol conversion for counter-current flow could be improved by 10%. This is due to the fact that counter-current flow leads to a better thermal management, which in turn improves fuel conversion efficiency. The results also reveal that the appropriate geometric parameters exist for a micro-reformer with a combustor to obtain better thermal management and methanol conversion. With a higher Reynolds number on the combustor side, the wall temperature is increased and the methanol conversion can thus be enhanced. In addition, the three-dimensional models of a plate methanol steam micro-reformer and a methanol catalytic combustor with the parallel flow field and the serpentine flow field have been established to investigate the performance and transport phenomena in the micro-reformer. The methanol conversion of the micro-reformer with the serpentine flow field and the combustor with the serpentine flow field is the best due to a better thermal management in the micro-reformer. The numerical model provides an efficient way to characterize the transport phenomena within the micro-reformer, and the results will benefit the future design for the plate methanol steam micro-reformer.

博士 / 國立交通大學 / 機械工程學系 / 98 / The effects of adding Polythene (PE) in (polystyrene) PS foaming material on the cell structure and the heat transfer of vacuum insulation panels (VIPs) are examined in this study. Totally 42 samples were fabricated and analyzed to examine the influence of porous foam structure and PE additive on VIP performance. The samples were produced by in-house equipment that was able to vary the foam structure by modulating the process temperature and pressure. Several parameters were proposed to describe the foam structure, namely, the broken cell ratio, the average cell size and the solid volume fraction. Under a specific solid volume fraction, the average cell size and the broken cell ratio are linearly correlated, and it was found that an optimum cell size exists such that the total heat transport is minimal. Furthermore, these parameters are also suitable for characterizing heat transfer coefficients of thermal radiation and other heat transports. Adding 2% PE was effective in altering the cell structure and reducing the heat transfer, while adding 5% PE did not improve the performance further. The lowest thermal conductivity found in this study is 4.4 , which is among the best published performances of VIP. The magnitude of solid conduction is mainly decided by the solid volume fraction and accounts for more than 80% of the total heat transport in VIPs. The rule of thumb of reducing VIPs’ heat transport is to decrease the solid volume fraction as much as possible, while maintaining an optimal average cell size. Nevertheless, attention should be paid to balancing solid conduction and thermal radiation. The reduction of solid volume fraction is normally accompanied by the decrease of solid mass, leading to weaker structural support such that smaller cell size is required to maintain structure integrity. The decrease of solid mass is therefore accompanied by slimmer struts and thinner membrane, which may largely enhance thermal radiation.