Ternary content addressable memories (TCAMs) are hardware-based parallel lookup tables with bit-level masking capability. They are attractive for applications such as packet forwarding and classification in network routers. Despite the attractive features of TCAMs, high power consumption is one of the most critical challenges faced by TCAM designers. This work proposes circuit techniques for reducing TCAM power consumption. The main contribution of this work is divided in two parts: (i) reduction in match line (ML) sensing energy, and (ii) static-power reduction techniques. The ML sensing energy is reduced by employing (i) positive-feedback ML sense amplifiers (MLSAs), (ii) low-capacitance comparison logic, and (iii) low-power ML-segmentation techniques. The positive-feedback MLSAs include both resistive and active feedback to reduce the ML sensing energy. A body-bias technique can further improve the feedback action at the expense of additional area and ML capacitance. The measurement results of the active-feedback MLSA show 50-56% reduction in ML sensing energy. The measurement results of the proposed low-capacitance comparison logic show 25% and 42% reductions in ML sensing energy and time, respectively, which can further be improved by careful layout. The low-power ML-segmentation techniques include dual ML TCAM and charge-shared ML. Simulation results of the dual ML TCAM that connects two sides of the comparison logic to two ML segments for sequential sensing show 43% power savings for a small (4%) trade-off in the search speed. The charge-shared ML scheme achieves power savings by partial recycling of the charge stored in the first ML segment. Chip measurement results show that the charge-shared ML scheme results in 11% and 9% reductions in ML sensing time and energy, respectively, which can be improved to 19-25% by using a digitally controlled charge sharing time-window and a slightly modified MLSA. The static power reduction is achieved by a dual-VDD technique and low-leakage TCAM cells. The dual-VDD technique trades-off the excess noise margin of MLSA for smaller cell leakage by applying a smaller VDD to TCAM cells and a larger VDD to the peripheral circuits. The low-leakage TCAM cells trade off the speed of READ and WRITE operations for smaller cell area and leakage. Finally, design and testing of a complete TCAM chip are presented, and compared with other published designs.

With CMOS technology scaling reaching its limitations rigorous research of alternate and competent technologies is paramount to push the boundaries of computing. Spintronic and resistive memories have proven to be effective alternatives in terms of area, power and performance to CMOS because of their non-volatility, ability for logic computing and easy integration with CMOS. However, deeper investigations to understand their physical phenomenon and improve their properties such as writability, stability, reliability, endurance, uniformity with minimal device-device variations is necessary for deployment as memories in commercial applications. Application of these technologies beyond memory and logic are investigated in this thesis i.e. for security of integrated circuits and systems and special purpose memories. We proposed a spintonic based special purpose memory for search applications, present design analysis and techniques to improve the performance for larger word lengths upto 256 bits. Salient characteristics of RRAM is studied and exploited in the design of widely accepted hardware security primitives such as Physically Unclonable Function (PUF) and True Random Number Generators (TRNG). Vulnerability of these circuits to adversary attacks and countermeasures are proposed. Proposed PUF can be implemented within 1T-1R conventional memory architecture which offers area advantages compared to RRAM memory and cross bar array PUFs with huge number of challenge response pairs. Potential application of proposed strong arbiter PUF in the Internet of things is proposed and performance is evaluated theoretically with valid assumptions on the maturity of RRAM technology. Proposed TRNG effectively utilizes the random telegraph noise in RRAM current to generate random bit stream. TRNG is evaluated for sufficient randomness in the random bit stream generated. Vulnerability and countermeasures to adversary attacks are also studied. Finally, in thesis we investigated and extended the application of emerging non-volatile memory technologies for search and security in integrated circuits and systems.

The Catalyst 6500 is a modern commercial switch, capable of processing millions of packets per second through the utilization of specialized hardware. One of the main hardware components aiding the switch in performing its task is the Ternary Content Addressable Memory (TCAM). TCAMs update themselves with data relevant to routing and switching based on the traffic flowing through the switch. This enables the switch to forward future packets destined to a location that has already been previously discovered - at a very high speed. The problem is TCAMs have a limited size, and once they reach their capacity, the switch has to rely on software to perform the switching and routing - a much slower process than performing Hardware Switching that utilizes the TCAM. A framework has been developed to analyze the switch’s performance once the TCAM has reached its capacity, as well as measure the penalty associated with a cache miss. This thesis concludes with some recommendations and future work.

The Catalyst 6500 is a modern commercial switch, capable of processing millions of packets per second through the utilization of specialized hardware. One of the main hardware components aiding the switch in performing its task is the Ternary Content Addressable Memory (TCAM). TCAMs update themselves with data relevant to routing and switching based on the traffic flowing through the switch. This enables the switch to forward future packets destined to a location that has already been previously discovered - at a very high speed. The problem is TCAMs have a limited size, and once they reach their capacity, the switch has to rely on software to perform the switching and routing - a much slower process than performing Hardware Switching that utilizes the TCAM. A framework has been developed to analyze the switch’s performance once the TCAM has reached its capacity, as well as measure the penalty associated with a cache miss. This thesis concludes with some recommendations and future work.

The performance of a modern computing system is improving with technology scaling due to advancements in the modern semiconductor industry. However, the power efficiency along with reliability does not scale linearly with performance efficiency. High leakage and standby power in sub 100 nm technology are critical challenges faced by circuit designers. Recent developments in device physics have shown that emerging non-volatile memories are very effective in reducing power dissipation because they eliminate stand by power and exhibit almost zero leakage powerThis dissertation studies the use of emerging non-volatile memory devices in designing circuit architecture for improving power dissipation and the performance of the computing system. More specically, it proposes a novel spintronic Ternary Content AddressableMemory (TCAM), a novel memristive TCAM with improved power and performance efficiency. Our experimental evaluation on 45 nm technology for a 256-bit word-size spintronic TCAM at a supply voltage of 1 V with a sense margin of 50 mV show that the delay is lessthan 200 ps and the per-bit search energy is approximately 3 fJ. The proposed spintronic TCAM consumes at least 30% less energy when compared to state-of-the-art TCAM designs. The search delay on a 144-bit proposed memristive TCAM at a supply voltage of 1 V and a sense margin of 140 mV is 175 ps with per bit search energy of 1.2 fJ on a 45 nm technology. It is 1.12 x times faster and dissipates 67% less search energy per bit than the fastest existing 144-bit MTCAM design.Emerging non-volatile memories are well known for their ability to perform fast analog multiplication and addition when they are arranged in crossbar fashion and are especially suited for neural network applications. However, such systems require the on-chip implementation of the backpropagation algorithm to accommodate process variations. This dissertation studies the impact of process variation in training memristive neural network architecture. It proposes a low hardware overhead on-chip implementation of the backpropagation algorithm that utilizes effectively the very dense memristive cross-bar arrayand is resilient to process variations.Another important issue that needs a careful study due to shrinking technology node is the impact of space or terrestrial radiation in Integrated Circuits (ICs) because the probability of a high energy particle causing an error increases with a decrease in thethreshold voltage and the noise margin. Moreover, single-event effects (SEEs) sensitivity depends on the set of input vectors used at the time of testing due to logical masking. This dissertation analyzes the impact of input test set on the cross section of the microprocessorand proposes a mechanism to derive a high-quality input test set using an automatic test pattern generation (ATPG) for radiation testing of microprocessors arithmetic and logical units..

Vaccines have saved more lives than any other medical intervention. Recombinant vaccines provide unmatched safety profiles, but at the expense of reduced immunogenicity. Virus-like particles (VLPs) resemble viruses in size, shape and repetitive arrangement but are devoid of pathogenic genetic material and therefore safe. Poor immunogens can be rendered immunogenic by display on VLPs. Successfully decorating VLPs is still a major challenge. Genetic fusion or chemical modification is often time-consuming and can lead to misassembly or misfolding, which obstructs generation of the desired immune response. SpyCatcher is a genetically encodable protein, previously engineered to form a covalent isopeptide bond to its peptide-partner SpyTag. Presented in this thesis are SpyCatcher-VLPs, based on the fusion of SpyCatcher to the bacteriophage VLP AP205. SpyCatcher- VLPs can be conveniently conjugated with SpyTag fused antigens, simply by mixing. I demonstrate the modularity of this approach by covalently linking several complex, cysteine-rich malarial antigens to SpyCatcher-VLPs, such as the transmission-blocking antigen Pfs25 and the blood-stage antigen CIDR. A single administration of Pfs25-SpyTag conjugated to SpyCatcher-VLPs induced potent antibody generation against Pfs25, even in the absence of adjuvant. Anti-Pfs25 antibodies induced by this platform conveyed potent transmission-blocking activity in the mosquito vector. The thesis further demonstrates the feasibility of more complex Catcher-nanoparticle architectures. The previously engineered SnoopCatcher covalently reacts with SnoopTag peptide and is orthogonal to the SpyCatcher / SpyTag pair. IMX313 is an engineered chimera of the multimerization domain of chicken complement inhibitor C4-binding protein. This work describes fusion of SnoopCatcher and SpyCatcher to IMX313, which yields independently addressable Catcher-moieties on a single IMX313 nanoparticle. Display of two antigens on one particle may enable single-particle, multi-disease vaccines as well as multi-stage vaccines to tackle immune evasion of parasites. The platforms presented should accelerate and enhance vaccine development and may create opportunities for imaging and metabolic engineering.

This dissertation investigates and introduces novel algorithms, theories, and supporting frameworks to significantly improve the growing problem of Internet security. A distributed firewall and active response architecture is introduced that enables any device within a cyber environment to participate in the active discovery and response of cyber attacks. A theory of semantic association systems is developed for the general problem of knowledge discovery in data. The theory of semantic association systems forms the basis of a novel semantic path merger packet classification algorithm. The theoretical aspects of the semantic path merger packet classification algorithm are investigated, and the algorithm's hardware-based implementation is evaluated along with comparative analysis versus content addressable memory. Experimental results show that the hardware implementation of the semantic path merger algorithm significantly outperforms content addressable memory in terms of energy consumption and operational timing.

The master’s thesis „Support for instruction in electric fire alarm system” describes principles and engineering solution of electric fire alarm system. It is background for activity task about EPS for students in VUT in Brno. It illustrates how to act on this task and configuration fire panel and components EPS with the support of software FSP 5000. The practice contains proposal EPS with support in fire system designer.