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FPGA clock frequencies are slow enough that only a fraction of the interconnect’s bandwidth is used. By exploiting this bandwidth, the transfer of large amounts of data can be greatly accelerated. Alternatively, it may also be possible to save area on fixed-bandwidth links by using on-chip serial signaling. For datapath-intensive designs which operate on words instead of bits, this can reduce wiring congestion as well. This thesis proposes relatively simple circuit-level modifications to FPGA interconnect to enable high-bandwidth communication. High-level area estimates indicate a potential interconnect area savings of 10 to 60% when serial links are used. Two interconnect pipelining techniques, wave pipelining and surfing, are adapted to FPGAs and compared against each other and against regular FPGA interconnect in terms of throughput, reliability, area, power, and latency. Source-synchronous signaling is used to achieve high data rates with simple receiver design. Statistical models for high-frequency power supply noise are developed and used to estimate the probability of error of wave pipelined and surfing links as a function of link length and operating speed. Surfing is generally found to be more reliable and less sensitive to noise than wave pipelining. Simulation results in a 65nm process demonstrate a throughput of 3Gbps per wire across a 50-stage, 25mm link.

In this thesis we discuss how to find equivalent representations of polynomial functions over the ring of integers modulo a power of a prime. Specifically, we look for lower degree representations and representations with fewer variables for which important applications in electrical and computer engineering exist. We present several algorithms for finding these compact formulations.

This thesis investigates techniques for the automated optimization of quantum circuits. In the first part we develop an exponential time algorithm for synthesizing minimal depth quantum circuits. We combine this with effective heuristics for reducing the search space, and show how it can be extended to different optimization problems. We then use the algorithm to compute circuits over the Clifford group and T gate for many of the commonly used quantum gates, improving upon the former best known circuits in many cases. In the second part, we present a polynomial time algorithm for the re-synthesis of CNOT and T gate circuits while reducing the number of phase gates and parallelizing them. We then describe different methods for expanding this algorithm to optimize circuits over Clifford and T gates.

Chip temperature is increasing with continued technology scaling due to increased power density and decreased device feature sizes. Since temperature has significant impact on performance and reliability, accurate thermal and circuit analysis are of great importance. Due to the shrinking device feature size, effects occurring at the nanometre scale, such as ballistic transport of energy carriers and electron tunneling, have become increasingly important and must be considered. However, many existing thermal and circuit analysis methods are not able to consider these effects efficiently, if at all. This thesis presents methods for accurate and efficient multi-scale thermal and circuit analysis. For circuit analysis, the simulation of single-electron device circuits is specifically studied. To target thermal analysis, in this work, ThermalScope, a multi-scale thermal analysis method for nanometre-scale IC design is developed. It unifies microscopic and macroscopic thermal physics modeling methods, i.e., the Boltzmann transport and Fourier modeling methods. Moreover, it supports adaptive multi-resolution modeling. Together, these ideas enable efficient and accurate characterization of nanometre-scale heat transport as well as chip-package level heat flow. ThermalScope is designed for full chip thermal analysis of billion-transistor nanometre-scale IC designs, with accuracy at the scale of individual devices. ThermalScope has been implemented in software and used for full chip thermal analysis and temperature-dependent leakage analysis of an IC design with more than 150 million transistors. To target circuit analysis, in this work, SEMSIM, a multi-scale single-electron device simulator is developed with an adaptive simulation technique based on the Monte Carlo method. This technique significantly improves the time efficiency while maintaining accuracy for single-electron device and circuit simulation. It is shown that it is possible to reduce simulation time up to nearly 40 times and maintain an average propagation delay error of under 5% compared to a non-adaptive Monte Carlo method. This simulator has been used to handle large circuit benchmarks with more than 6000 junctions, showing efficiency comparable to SPICE, with much better accuracy. In addition, the simulator can characterize important secondary effects including cotunneling and Cooper pair tunneling, which are critical for device research. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2008-09-26 13:33:12.389

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This research attempts to quantify the complex interactions between HVDC transmission schemes in a multi-infeed configuration, particularly with regard to the voltage interactions and the commutation failure phenomena. The in-depth analysis of multi-infeed HVDC systems discussed in this research shows the application of several indices such as the MIIF, MIESCR, and CFII, that can provide researchers and planning engineers in the area of HVDC transmission with the necessary tools for their system studies. It shows that these indices are applicable in a multi-infeed system comprising HVDC schemes with different ratings. The Multi-Infeed Interaction Factor (MIIF) quantifies the level of voltage interactions between converter ac buses. The Multi-Infeed Effective Short Circuit Ratio (MIESCR) index is an indicator of ac system strengths with regard to the assessment of the transient overvoltage (TOV) and the power-voltage stability of multi-infeed HVDC systems. The Commutation Failure Immunity Index (CFII) utilizes electromagnetic transient simulation programs to evaluate the immunity of an HVDC converter to commutation failures. The CFII takes into account the ac system strength and the HVDC controls and evaluates their impact on the commutation process. The immunity of both single-infeed and multi-infeed systems to commutation failure phenomena are accurately evaluated and quantified by the CFII. Using the CFII, it is shown that the current commutation in multi-infeed HVDC schemes could fail under circumstances in which the probability of failure had been perceived to be low. The causes of, the effects of, and the remedial actions needed to deal with such anomalous commutation failures are discussed in this thesis. The capability of the new indices to provide an insight into the interactions phenomena in multi-infeed systems are clearly demonstrated by examples that show their application in the analysis of an actual multi-infeed HVDC system that is in the planning phase in the province of Alberta in Canada.

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