Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1980. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING. / Includes bibliographical references. / by John Newland Ratzel. / Ph.D.

by Wong Yin Shung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2005. / Includes bibliographical references (leaves 62-64). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.7 / Chapter 2 --- Fundamentals --- p.9 / Chapter 2.1 --- Representation of a digital image --- p.9 / Chapter 2.2 --- Salt-and-pepper --- p.10 / Chapter 2.3 --- Resolution of a gray digital image --- p.11 / Chapter 3 --- Filters --- p.14 / Chapter 3.1 --- Median filter --- p.15 / Chapter 3.2 --- Adaptive median filter --- p.15 / Chapter 3.3 --- Multi-state median filter --- p.16 / Chapter 3.4 --- Directional difference-based switching median filter --- p.18 / Chapter 3.5 --- Improved switching median filters --- p.20 / Chapter 3.6 --- Variational method --- p.21 / Chapter 3.7 --- Two-phase method --- p.22 / Chapter 4 --- New Two Phase Methods --- p.25 / Chapter 4.1 --- Triangule-based interpolation --- p.25 / Chapter 4.1.1 --- Delaunay triangulation --- p.26 / Chapter 4.1.2 --- Linear interpolation --- p.28 / Chapter 4.1.3 --- Cubic interpolation --- p.29 / Chapter 4.2 --- Gradient estimation --- p.32 / Chapter 4.3 --- Regularization method --- p.33 / Chapter 4.3.1 --- Least square method with Laplacian regularization --- p.33 / Chapter 4.3.2 --- Lagrange multipliers --- p.35 / Chapter 4.4 --- Fast transform for finding the inverse of Laplacian matrix --- p.38 / Chapter 5 --- Inpainting and Zooming --- p.39 / Chapter 5.1 --- Inpainting --- p.39 / Chapter 5.2 --- Zooming --- p.40 / Chapter 5.2.1 --- Bilinear interpolation --- p.40 / Chapter 5.2.2 --- Bicubic interpolation --- p.41 / Chapter 6 --- Results --- p.46 / Chapter 6.1 --- Results of denoising --- p.47 / Chapter 6.2 --- Results of inpainting --- p.47 / Chapter 6.3 --- Results of zooming --- p.48 / Chapter 6.4 --- Conclusions --- p.51

Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Aeronautics and Astronautics, 1981. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND AERONAUTICS. / Bibliography: p. 235-239. / by Jere Schenck Meserole, Jr. / Ph.D.

Thesis. 1978. Ph.D.--Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING. / Vita. / Includes bibliographical references. / by Joseph Edward Wall, Jr. / Ph.D.

[by] Bernard Gold and Lawrence R. Rabiner. / Bibliography: p. 36. / Contract DA 28-043-AMC-02536(E). Project no. 200-14501-B31F.

Digital filters having sharp transition band play a vital role in modern digital signal processing (DSP) applications. Emerging technologies require digital filters to be both computationally efficient in software/hardware realizations. This thesis is concerned with the design and structural-level optimization of sharp transition band digital filters employing the well known frequency response masking (FRM) approach. Unlike the conventional finite impulse response (FIR) based FRM approach, the FRM technique used in this thesis incorporates infinite impulse response (IIR) digital interpolation subfilters, thereby reducing the overall filter order that results in a reduction of hardware complexity. Two realization methods are discussed in this thesis, namely, the bilinear-lossless-discrete-integrators (bilinear-LDI) digital filter design technique, and the lattice wave digital filter (lattice WDF) digital filter design technique. Diversity controlled (DC) genetic algorithm (GA) is employed to optimize both types of IIR based FRM digital filters over the efficient canonical signed digit (CSD) multiplier coefficient space. DCGAs represent FRM digital filters by a binary chromosome and proceed from a population pool of candidate chromosomes to future generations in order to arrive at the desired FRM digital filter satisfying the design specifications. A novel cost-function is used that allows the DCGA to simultaneously optimize both the amplitude-frequency and group-delay frequency response. A fast convergence speed has been observed. / Communications

In this thesis two versions of a single filter frequency masking narrow-band high-speed recursive digital filter structure, proposed in [1], have been implemented and evaluated considering the maximal clock frequency, the maximal sample frequency and the power consumption. The structures were compared to a conventional filter structure, that was also implemented. The aim was to see if the proposed structure had some benefits when implemented and synthesized, not only in theory. For the synthesis standard cells from AMS csx 0.35 mm CMOS technology were used.

The IEEE 802.3aq standard recommends a multi-tap decision feedback equalizer be implemented to remove inter-symbol interference and additive system noise from data transmitted over a 10 Gigabit per Second (10 Gbps) multi-mode fiber-optic link (MMF). The recommended implementation produces a design in an analog process. This design process is difficult, time consuming, and is expensive to modify if first pass silicon success is not achieved. Performing the majority of the design in a well-characterized digital process with stable, evolutionary tools reduces the technical risk. ASIC design rule checking is more predictable than custom tools flows and produces regular, repeatable results. Register Transfer Language (RTL) changes can also be relatively quickly implemented when compared to the custom flow. However, standard cell methodologies are expected to achieve clock rates of roughly one-tenth of the corresponding analog process. The architecture and design for a parallel linear equalizer and decision feedback equalizer are presented. The presented design demonstrates an RTL implementation of 10 GHz filters operating in parallel at 625 MHz. The performance of the filters is characterized by testing the design against a set of 324 reference channels. The results are compared against the IEEE standard group s recommended implementation. The linear equalizer design of 20 taps equalizes 88 % of the reference channels. The decision feedback equalizer design of 20 forward and 1 reverse tap equalizes 93 % of the reference channels. Analysis of the unequalized channels in performed, and areas for continuing research are presented.

<p>In this thesis two versions of a single filter frequency masking narrow-band high-speed recursive digital filter structure, proposed in [1], have been implemented and evaluated considering the maximal clock frequency, the maximal sample frequency and the power consumption. The structures were compared to a conventional filter structure, that was also implemented. The aim was to see if the proposed structure had some benefits when implemented and synthesized, not only in theory. For the synthesis standard cells from AMS csx 0.35 mm CMOS technology were used.</p>

Thesis (Ph. D.)--York University, 2001. Graduate Programme in Computer Science. / Typescript. Includes bibliographical references (leaves 132-142). Also available on the Internet. MODE OF ACCESS via web browser by entering the following URL: http://wwwlib.umi.com/cr/yorku/fullcit?pNQ66340