O presente trabalho de doutorado tem por objetivo a criação de uma nova família de filtros digitais específica para o processo de classificação de dados, particularmente aplicada ao pré-diagnóstico de patologias na laringe. Antes de explicar a criação dessa nova família de filtros, foi apresentada uma breve revisão bibliográfica sobre o funcionamento do aparelho fonador humano, sobre o processo de diagnóstico de patologias e sobre a transformada discreta Wavelet, que serviu de base para a construção dos filtros propostos. Em seguida, é descrita a tecnologia proposta para a criação da nova família de filtros, que é baseada na construção da Transformada Wavelet de Daubechies, além disso, apresenta-se uma breve comparação com outras técnicas já descritas na literatura para a mesma finalidade. Posteriormente, são apresentados os resultados obtidos com base na técnica proposta, verificando-se uma taxa de acerto na classificação de vozes normais de 100% e uma taxa de acerto de 95,52% para vozes patológicas. / The main purpose of this thesis is the development of a new family of digital filters used for data classification, particularly applied to the pre-diagnosis of pathologies in the larynx. A brief bibliographical review, that concentrates on the functioning of the human vocal tract, on the process of disease diagnosis, and on the discrete wavelet transform, which formed the basis for the construction of the proposed filters, is presented. The technology used to develop these new families of filters, that is based on the Daubechies Wavelet Transform, is also described, moreover, a comparison with other techniques described in the specialized literature for the same purpose is also presented. The investigation shows the results obtained with the proposed technique, in which the accuracy of 100% in normal voice classifications and of 95,52% in pathological voice classifications, was obtained.

A aquisição de sinais cerebrais de bovinos adultos, utilizando um equipamento de transmissão telemétrica dos dados e eletrodos de superfície, foi avaliada neste trabalho através de técnicas de processamento digital de sinais. Foram estudados a melhor disposição dos eletrodos, diferentes métodos de remoção de artefatos e as características em freqüência do sinal. A remoção de artefatos foi feita de duas maneiras: (1) uso de um filtro que substituía valores extremos do sinal por seu valor médio e (2) decomposição utilizando a capacidade de multiresolução das ondaletas. Os resultados obtidos mostraram que apenas trechos de sinal livres de artefatos podem ser processados. O processamento indicou faixas de freqüências em acordo com a literatura. A metodologia usada neste trabalho mostrou-se suficiente para concluir que é possível monitorar e analisar sinais cerebrais de bovinos adultos que podem se mover livremente, sem acrescentar ao experimento o estresse característico de contenção / Acquisition of brain electrical activity from grown bovines, using a telemetric data transmitter system and scalp electrodes, was evaluated in this work. Electrodes placement, different artifact removal methodologies and signal frequency component were studied. Artifacts removal was carried out in two different ways: (1) by means of a filter that replaced elevated amplitude points for the signal’s mean value and (2) decomposition using wavelet multiresolution capability. Results using filters show that only artifact-free signal stretches can be processed. The processing indicated that frequency ranges are in agreement with literature. The methodology applied in this work is enough to conclude that it is possible to analyze brain electrical signal from grown bovines that can move freely, without add restrain stress factors to experiment

<p>The advancements of computational power in low cost FPGAs are giving the opportunityto implement real-time compensation of loudspeakers and audio systems. The need for expensive commercial audio systems is reduced when the fidelity ofmuch cheaper audio systems easily can be improved by real-time compensation. The topic of this thesis is to investigate and evaluate methods for digital compensationof distortion in audio systems. More specifically, a VHDL module isimplemented to, when necessary, alleviate the problem of drastically deterioratingfidelity of the bass appearing when the input power is too high.</p>

On this thesis project, the LMS algorithm has been applied for speech noise filteringand different behaviors were tested under different circumstances by using Matlabsimulations and the LPC2378 ARM Processor, which does the task of filtering in realtime. The thesis project is divided into two parts: the theoretical and practical part. In the theoretical part there is a brief description of the different aspects of signalprocessing systems, filter theory, and a general description of the Least-Mean-SquareAdaptive Filter Algorithm. In the practical part of the report a general description of the procedure will besummarized, the results of the tests that were conducted will be analyzed, a generaldiscussion of the problems that were encounter during the simulations will be mention,and suggestion for the problems will be given.

The advancements of computational power in low cost FPGAs are giving the opportunityto implement real-time compensation of loudspeakers and audio systems. The need for expensive commercial audio systems is reduced when the fidelity ofmuch cheaper audio systems easily can be improved by real-time compensation. The topic of this thesis is to investigate and evaluate methods for digital compensationof distortion in audio systems. More specifically, a VHDL module isimplemented to, when necessary, alleviate the problem of drastically deterioratingfidelity of the bass appearing when the input power is too high.

<p>On this thesis project, the LMS algorithm has been applied for speech noise filteringand different behaviors were tested under different circumstances by using Matlabsimulations and the LPC2378 ARM Processor, which does the task of filtering in realtime. The thesis project is divided into two parts: the theoretical and practical part.</p><p>In the theoretical part there is a brief description of the different aspects of signalprocessing systems, filter theory, and a general description of the Least-Mean-SquareAdaptive Filter Algorithm.</p><p>In the practical part of the report a general description of the procedure will besummarized, the results of the tests that were conducted will be analyzed, a generaldiscussion of the problems that were encounter during the simulations will be mention,and suggestion for the problems will be given.</p>

Digital signal processing (DSP) is widely used in many applications spanning the spectrum from audio processing to image and video processing to radar and sonar processing. At the core of digital signal processing applications is the digital filter which are implemented in two ways, using either finite impulse response (FIR) filters or infinite impulse response (IIR) filters. The primary difference between FIR and IIR is that for FIR filters, the output is dependent only on the inputs, while for IIR filters the output is dependent on the inputs and the previous outputs. FIR filters also do not sur from stability issues stemming from the feedback of the output to the input that aect IIR filters. In this thesis, an architecture for FIR filtering based on distributed arithmetic is presented. The proposed architecture has the ability to implement large FIR filters using minimal hardware and at the same time is able to complete the FIR filtering operation in minimal amount of time and delay when compared to typical FIR filter implementations. The proposed architecture is then used to implement the fast affine projection adaptive algorithm, an algorithm that is typically used with large filter sizes. The fast affine projection algorithm has a high computational burden that limits the throughput, which in turn restricts the number of applications. However, using the proposed FIR filtering architecture, the limitations on throughput are removed. The implementation of the fast affine projection adaptive algorithm using distributed arithmetic is unique to this thesis. The constructed adaptive filter shares all the benefits of the proposed FIR filter: low hardware requirements, high speed, and minimal delay.

In this thesis we describe a method of mapping one-dimensional and multidimensional filter algorithms onto systolic architectures using the z-domain approach. In this approach the filter algorithm is first transformed into its corresponding z-domain equivalent and recursive expressions similar to single assignment codes are derived using Horner's rule or other polynomial evaluation techniques. By obtaining different recursive expressions, different systolic structures can be derived. The characteristics of these structures can easily be deduced from the recursive expressions. The multidimensional filters derived are modular and hierarchical, i.e., the three-dimensional structures are obtained from the two-dimensional ones which are in turn obtained from one-dimensional structures. In considering the design of any array processor, it is important to consider the design of the processing elements involved. The most important and demanding operation in these elements is the multiplication. Four different multipliers are designed in which the number of operations required to produce the desired result is reduced. The reduced number of operations along with the advantages of very-large-scale integration technology in terms of increased device density and faster switching make these multipliers potential candidates in high-speed signal processing applications. The first multiplier is an area-efficient multiplier that uses approximately 50% of the area of a full parallel multiplier. In this multiplier only the units yielding the most significant part of the product are used. In addition, a correction unit is incorporated to minimize the error resulting from circumventing the use of units yielding the least significant part of the product. The second multiplier is based on the modified octal Booth algorithm in which four-bit segments of the multiplier are scanned and corresponding operations effected on the multiplicand. The third multiplier is a diminished-1 multiplier that finds application in the Fermat number-theoretic transform. In this multiplier the use of a translator is circumvented and a novel technique for translation is incorporated in the multiplier structure. The fourth multiplier is one that performs an inner-product operation without the use of an accumulator thereby resulting in increased speed and reduced area. Finally we discuss the VLSI implementations of three of the multipliers mentioned above, a second-order digital filter, and a single processing element that can be used as a basic unit in designing one-dimensional and multidimensional digital filters. Some associated problems in digital-filter structure. viz., the quantization and overflow limit-cycle oscillations; have been taken into consideration and ways have been suggested for their elimination. / Graduate

Les FPGA (Field Programmable Gate Arrays) constituent un type de circuit reprogrammable qui, sous certaines conditions, peuvent avoir de meilleures performances que les microprocesseurs classiques. Les FPGA utilisent le circuit comme paradigme de programmation, ce qui permet d'effectuer des calculs parallèles propres à l'application visée. Ils permettent aussi d’atteindre l’efficacité arithmétique: un bit ne doit être calculé que s'il est utile dans le résultat final. Pour ce faire, l’arithmétique utilisée par les FPGA ne peut se limiter qu’à des fonctions conçues pour les microprocesseurs. Cette thèse se propose d’étudier les méthodes pour l’implémentation des fonctions gros-grain pour les FPGA à travers trois voies. De nouvelles méthodes pour évaluer des fonctions trigonométriques, telles que le sinus, cosinus et arc tangente ont été développés dans cette thèse. Chaque méthode est optimisée dans son contexte, de la manière la plus flexible et la plus souple possible. Pour que les méthodes aboutissent à leur efficacité arithmétique, il est nécessaire de procéder à une analyse d'erreurs, ainsi qu’à un choix attentif des paramétrés de la méthode et à une fine compréhension des algorithmes utilisés. Les filtres numériques constituent une famille importante d’opérateurs arithmétiques qui rassemble des fonctions élémentaires. Ils peuvent être spécifiés à un niveau élevé d'abstraction, à travers une fonction de transfert avec des contraintes sur le rapport signal/bruit. Ils peuvent être ensuite implémentés comme des chemins de données basés sur des additions et des multiplications. Le principal résultat est donc une méthode qui transforme une spécification de haut niveau en une implémentation d’une façon automatique. La première étape se rapporte au développement d'une méthode pour le calcul des produits par des constantes. Des filtres FIR et IIR peuvent être construits à l'aide de cette brique de base. Pour que les opérateurs arithmétiques atteignent leur performance maximale, on a besoin d’un pipeline correspondant au contexte donné. Même si les connaissances du développeur s’avèrent d’un grand avantage pendant le processus de création d'un pipeline d'un chemin de données, cette étape demeure complexe et facilement susceptible à des erreurs. Une méthode automatique, contrôlée par le développeur a dont été développée. Cette thèse fournit un générateur des opérateurs arithmétiques de haute qualité près à l'emploi, et qui propagent le domaine des calculs sur des FPGA à un pas plus proche de l’adoption générale. Les cœurs arithmétiques font partie d'un générateur open-source, où les fonctions peuvent être décrites par une spécification de haut niveau, comme par exemple une formule mathématique. / Field-Programmable Gate Arrays (FPGAs) have been shown to sometimes outperform mainstream microprocessors. The circuit paradigm enables efficient application-specific parallel computations. FPGAs also enable arithmetic efficiency: a bit is only computed if it is useful to the final result. To achieve this, FPGA arithmetic shouldn’t be limited to basic arithmetic operations offered by microprocessors. This thesis studies the implementation of coarser operations on FPGAs, in three main directions: New FPGA-specific approaches for evaluating the sine, cosine and the arctangent have been developed. Each function is tuned for its context and is as versatile and flexible as possible. Arithmetic efficiency requires error analysis and parameter tuning, and a fine understanding of the algorithms used. Digital filters are an important family of coarse operators resembling elementary functions: they can be specified at a high level as a transfer function with constraints on the signal/noise ratio, and then be implemented as an arithmetic datapath based on additions and multiplications. The main result is a method which transforms a high-level specification into a filter in an automated way. The first step is building an efficient method for computing sums of products by constants. Based on this, FIR and IIR filter generators are constructed. For arithmetic operators to achieve maximum performance, context-specific pipelining is required. Even if the designer’s knowledge is of great help when building and pipelining an arithmetic datapath, this remains complex and error-prone. A user-directed, automated method for pipelining has been developed. This thesis provides a generator of high-quality, ready-made operators for coarse computing cores, which brings FPGA-based computing a step closer to mainstream adoption. The cores are part of an open-ended generator, where functions are described as high-level objects such as mathematical expressions.

A aquisição de sinais cerebrais de bovinos adultos, utilizando um equipamento de transmissão telemétrica dos dados e eletrodos de superfície, foi avaliada neste trabalho através de técnicas de processamento digital de sinais. Foram estudados a melhor disposição dos eletrodos, diferentes métodos de remoção de artefatos e as características em freqüência do sinal. A remoção de artefatos foi feita de duas maneiras: (1) uso de um filtro que substituía valores extremos do sinal por seu valor médio e (2) decomposição utilizando a capacidade de multiresolução das ondaletas. Os resultados obtidos mostraram que apenas trechos de sinal livres de artefatos podem ser processados. O processamento indicou faixas de freqüências em acordo com a literatura. A metodologia usada neste trabalho mostrou-se suficiente para concluir que é possível monitorar e analisar sinais cerebrais de bovinos adultos que podem se mover livremente, sem acrescentar ao experimento o estresse característico de contenção / Acquisition of brain electrical activity from grown bovines, using a telemetric data transmitter system and scalp electrodes, was evaluated in this work. Electrodes placement, different artifact removal methodologies and signal frequency component were studied. Artifacts removal was carried out in two different ways: (1) by means of a filter that replaced elevated amplitude points for the signal’s mean value and (2) decomposition using wavelet multiresolution capability. Results using filters show that only artifact-free signal stretches can be processed. The processing indicated that frequency ranges are in agreement with literature. The methodology applied in this work is enough to conclude that it is possible to analyze brain electrical signal from grown bovines that can move freely, without add restrain stress factors to experiment