As network bandwidth growing and voice coding enhancing, voice transmitted over the Packet-Based network environment can also have good quality compared to traditional telephone network. Therefore, the IP telephony services having a price advantage could gradually replace the traditional telecommunication services. However, in order to support both the traditional telecommunication services and IP phone services, it requires the devices which are capable of converting analogical telephony information such as voice and fax into packet data suitable for transmitting over IP. We therefore design and implement an IP phone equipment that can make SIP phone calls, and can support the exchange of the analogical traditional telephone voice and the digital voice packets over IP. In the hardware design point of view, we implement an IP phone set device in an embedded development platform using Infineon EASY5120 development kit, which uses a digital signal processor, called Vinetic®-2CPE (part number is PEB3332), to handle voice encoding and decoding, e.g., G.711 u/A law and G.723 compression, and RTP encapsulation and decapsulation. In the software architecture, we choose Linux as our embedded operation system under which there are lots of GNU open source software to feed our need and further to develop our own software components. In the process of this implementation, the software and hardware co-design takes up most of time, and we also face some VoIP application problems, e.g., SIP. We try to build up a VoIP system to figure out and solve these problems. And we hope that this actually applicable VoIP embedded system can be used as a testbed and verifying platform for VoIP applications.

High-performance reconfigurable computing has demonstrated its potential to accelerate demanding computational applications. Thus, the current trend is towards combining the microprocessor with the power of reconfigurable hardware in embedded system research area. However, integrating hardware and software that is the interface of communication is challenging. In this thesis, we present a methodology flow to improve the cohesion between hardware and software for reconfigurable embedded system design through IRES (I-link for Reconfigurable Embedded System), Hardware-Software integration platform. In IRES, we set up the platform and produce the Executor through I-link (Hardware-Software Integration Link). The Executor consists of tasks and hardware bitstreams which are provided by user design, bootloader and operation system which are provided by system, and PSPs (Program Segment Prefix) which are from the files given above. We initial the system through bootloader which will scan the PSPs of Executor to construct Task Control Block (TCB), Hardware Control Block (HCB) and Netlist IP Information Block (NIB) data structure. User can get the hardware information from those data structures, and communicate with hardware by using simple functions like ¡§read()¡¨ and ¡§write()¡¨. Then, the system transmits the data to and from multi-hardware through Hardware Management Unit (HMU) which also has data buffering ability. Finally, we successfully accomplish IRES Hardware-Software integration platform in HSCP, which is developed in our laboratory, and verify the feasibility of communication between hardware and software.

De nos jours, les systèmes embarqués temps-réels critiques intègrent de plus en plus de composants, et voient leur complexité augmenter. Les systèmes avioniques ont suivi cette évolution, voyant augmenter leurs processus de développement. Dès lors, les développeurs de plates-formes avioniques se sont tournés vers les méthodes de modélisation en avance de phase (i.e. en tout début de cycle de développement), afin d’anticiper les performances de celles-ci et aider à leur dimensionnement. Particulièrement, l’exploration de l’utilisation des ressources matérielles de la plate-forme par la partie applicative (l’ensemble des applications) est le point central de cette exploration des performances. Si les méthodes de modélisation actuelles offrent la possibilité de modéliser une plate-forme depuis les exigences jusqu’au niveau architectural, elles ne sont pas encore adaptées à la modélisation comportementale. Elles ne permettent donc pas l’étude du comportement et la comparaison de différentes architectures d’une plate-forme en avance de phase. Mes travaux de thèse ont pour but d’offrir un processus de modélisation et simulation de plate-forme avionique répondant à cette problématique. L’objectif est de compléter les méthodes de modélisation actuelles pour apporter une analyse plus fine des performances d’une plate-forme en avance de phase, et les comparer avec les exigences. Pour cela, nous proposons une approche en quatre étapes : i) une étape de modélisation des applications et d’extraction des stimuli applicatifs ; ii) une étape de modélisation architecturale du système basée sur AADL (Architecture Analysis and Design Language) et son annexe ARINC653 ; iii) une étape de génération d’un modèle comportemental de la partie matérielle et intergicielle du système en SystemC-TLM ; iv) une étape de simulation et d’analyses, où les stimuli applicatifs sont exécutés par le modèle comportemental, et les performances extraites comparées aux exigences système. Enfin, nous avons validé notre méthode sur un cas d’étude avionique que nous présenterons également. / Nowadays, real-time critical embedded systems are more and more complex due to an increase of the integrated components. Following that trend, avionic systems development complexity increases too. So early modeling processes are more and more used in order to anticipate on plat-forms performance and help sizing them. Particularly, hardware resources usage exploration is a key aspect for performance exploration. Current processes allow to model avionic platform from requirements to architectural level of abstraction, but they do not allow to model a behavioral avionic platform. Thus, they do not allow to explore the hardware resources usage of the platform, neither to compare some alternatives of architectures at early phase of development cycle. My PhD work presents our avionic platform modeling and simulation process that answer that problem. The goal is to complete current modeling processes to offer more accurate early performance analysis, and compare them with the system requirements. For that, we propose a for steps method : i) an application modeling and stimuli extraction step ; ii) an architectural modeling step, based on the AADL (Architecture Analysis and Design Language) and its ARINC653 annex ; iii) a behavioral execution platform model (hardware and middleware) generation step with SystemC-TLM ; iv) a simulation and analysis step, when performance are compared with system requirements. At last, we will present our validation part on an avionic case study.

To the general purpose microprocessors, we often need to change microprocessors¡¦ hardware architecture because of customized purpose. But already existing application program is incompatible to the new hardware architecture, and increase the product¡¦s development period. In this thesis, we discuss the modification of two kinds of hardware architecture, include new instruction set extension and change the size of datapath to deal with specific application. To the former, our laboratory develop a 32-bit microprocessor SYS32-TM, increase MME instruction set to deal with multimedia application. The latter, based on Thumb instruction set , we develop 16-bit microprocessor SYS16-TM, we modify its¡¦ datapath from 32-bit to 16-bit, we will show how to let already existing application program can execute on the new hardware architecture. In SYS32-TM, we use the way of inline assembly to embedded MME instruction set in C source code, we have to modify the assembler, define and parse the MME instruction set, so the assembler can recognize it. In SYS16-TM, we have sign extension and address offset problems, we have to modify the compiler backend¡¦s machine description to solve the sign extension and address offset instruction set behavior, and modify the library. To build SYS16-TM software environment, we have to set C Run Time Environment in Thumb mode, not support exchange between ARM mode and Thumb mode, and write the correct linker script, to set the program start address in 0x0000, to solve ARM¡¦s initial program start address in 0x8000. As a result, In SYS32-TM, we use assembler to identify the MME instruction set can embedded in existing C source code. In SYS16-TM, we execute the testbench include sorts, Hanoi, Fibonacci number etc, and use simulator to verify its¡¦ correctness.

International Telemetering Conference Proceedings / October 21, 2002 / Town & Country Hotel and Conference Center, San Diego, California / Embedded GIS in Intelligent Navigation System is a special information system. This paper puts forward several basic principles and constraints during design for Embedded GIS at first, and then analyzes the feature of embedded platform and the function of Intelligent Navigation System, and presents a realization scheme of Embedded GIS.

International Telemetering Conference Proceedings / October 21, 2002 / Town & Country Hotel and Conference Center, San Diego, California / This paper introduces the essential points for designing a navigating system, and describes the modules of a typical vehicle navigator. This paper also gives a practical navigator example. Some experience for design is also mentioned.

This thesis presents a new cross-platform graphics performance tool, GPTT (Graphics Performance Tuning Tool), which is designed for helping developers to find the performance bottleneck of their games or applications on embedded systems. The functions of performance tool are embedded into the standard graphics library, OpenGL ES, to achieve cross-platform. In order to verify the proposed tool, we also implement the OpenGL ES specification in addition to the tool itself. The performance tool is separated into visualization part and measurement part from which it successfully decreases the load in embedded system, while running the application. Via the tool it identifies many bottlenecks that can be improved.

Developing 3D application for low-performance embedded system often contains some limitations as hardware specifications (e.g. memory and processing efficiency). Existing OpenGL ES emulators are designed to provide the development environment for programmers, but these emulators often are lack of cross-platform performance tuning analysis for embedded systems and are only suitable for a designated hardware. In this thesis, we present an OpenGL ES emulator with performance tuning for developing 3D application of embedded systems without conforming to a specific hardware. It can further help programmers to emulate 3D application on PC for different development platforms.

Embedded systems can be found everywhere in our daily lives. Due to the great variety of embedded devices, the platform independent Java language provides a good solution for embedded system development. Java virtual machine (JVM) is the most critical component of all kinds of Java platforms. Hence, it is extremely important to study the special design of JVM for embedded systems. The key challenges of designing a successful JVM for embedded systems are energy efficiency, time predictability and performance, which are investigated in this dissertation, respectively. We first study the energy issue of JVM on embedded systems. With a cycle-accurate simulator, we study each stage of Java execution separately to test the effects of different configurations in both software and hardware. After that, an alternative Adaptive Optimization System (AOS) model is introduced, which estimated the cost/benefit using energy data instead of running time. We tuned the parameters of this model to study how to improve the dynamic compilation and optimization in Jikes RVM in terms of energy consumption. In order to further reduce the energy dissipation of JVM on embedded systems, we study adaptive drowsy cache control for Java applications, where JVM can be used to make better decision on drowsy cache control. We explore the impact of different phases of Java applications on the timing behavior of cache usage. Then we propose several techniques to adaptively control drowsy cache to reduce energy consumption with minimal impact on performance. It is observed that traditional Java code generation and instruction fetch path are not efficient. So we study three hardware-based code caching strategies, which attempt to write and read the dynamically generated Java code faster and more energy-efficiently. Time predictability is another key challenge for JVM on embedded systems. So we exploit multicore computing to reduce the timing unpredictability caused by dynamic compilation and adaptive optimization. Our goal is to retain high performance comparable to that of traditional dynamic compilation and, at the same time, obtain better time predictability for JVM. We study pre-compilation techniques to utilize another core more efficiently. Furthermore, we develop Pre-optimization on Another Core (PoAC) scheme to replace AOS in Jikes JVM, which is very sensitive to execution time variation and impacts time predictability greatly. Finally, we propose two new approaches that automatically parallelizes Java programs at run-time, in order to meet the performance challenge of JVM on embedded systems. These approaches rely on run-time trace information collected during program execution, and dynamically recompiles Java byte code that can be executed in parallel. One approach utilizes trace information to improve traditional loop parallelization, and the other parallelizes traces instead of loop iterations.

During the first aid process, when patients are threatened by poor medical conditions, ambulance paramedics are required to administer emergency treatment based on instruc- tions provided by a remote emergency doctor through voice communication. However, such voice communication is always limited in expressing abundant detailed information for the patient. This thesis presents a framework for a stereoscopic and intelligent telemedicine sys- tem that can provide 3D live video communication between paramedics and emergency doctors. The proposed system captures 3D video from the paramedic headset carried by the paramedics, transmits the video through wireless live streaming, and displays the video with a 3D effect for emergency doctors in the hospital. The video can be analyzed to extract information about the patient through embedded algorithm such as face de- tection algorithm. In this thesis, the hardware, functional mechanism and face detection algorithm are introduced separately. The hardware of the system consists of a paramedic headset, a server box and a 3D PC, which are used to capture 3D video, transmit video through live streaming and display video with a stereo effect, respectively. The functional mechanism includes two subsystems, which work for pushing the stereo video to multiple live streams and displaying the 3D video from the live stream. In order to detect the patient information from the video, a multi-task face detection algorithm is applied to analyze the stereo video using deep learning technology. We improved the neural networks of face detection by utilizing 1 ⇥ 1 convolutional layers and retrain the network based on the transfer learning to achieve better and faster performance. This system has achieved good and stable performance in network delay (0.0489ms) and objective video quality evaluations. The face detection algorithm has achieved no- table accuracy (91.78% In FDDB dataset) and efficiency (19.71 ms/frame).