Weed control is nowadays a hi-tech discipline. Inter-row weed control is very sophisticated whereas the intra-row weed control lacks a lot. The aim of this pro ject is to implement an embedded system of an autonomous vision based intra-row weeding robot. Weed and crops can be distinguished due to several attributes like colour, shape and context fea- tures. Using an emebedded system has several advantages. The embedded system is specialized on video processing and is designed to withstand the needs of outdoor use. This embedded system is already able to distinguish between weed and crops. The per- formance of the hardware is very good whereas the software still needs some optimizations.

Cardiologists can gain useful insight into a patient's condition when they are able to correlate the patent's symptoms and activities. For this purpose, a Holter Monitor is often used - a portable electrocardiogram (ECG) recorder worn by the patient for a period of 24-72 hours. Preferably, the monitor is not cumbersome to the patient and thus it should be designed to be as small and light as possible; however, the storage requirements for such a long signal are very large and can significantly increase the recorder's size and cost, and so signal compression is often employed. At the same time, the decompressed signal must contain enough detail for the cardiologist to be able to identify irregularities. "Lossy" compressors may obscure such details, where a "lossless" compressor preserves the signal exactly as captured.<p>The purpose of this thesis is to develop a platform upon which a Holter Monitor can be built, including a hardware-assisted lossless compression method in order to avoid the signal quality penalties of a lossy algorithm. <p>The objective of this thesis is to develop and implement a low-complexity lossless ECG encoding algorithm capable of at least a 2:1 compression ratio in an embedded system for use in a Holter Monitor. <p>Different lossless compression techniques were evaluated in terms of coding efficiency as well as suitability for ECG waveform application, random access within the signal and complexity of the decoding operation. For the reduction of the physical circuit size, a System On a Programmable Chip (SOPC) design was utilized. <p>A coder based on a library of linear predictors and Rice coding was chosen and found to give a compression ratio of at least 2:1 and as high as 3:1 on real-world signals tested while having a low decoder complexity and fast random access to arbitrary parts of the signal. In the hardware-assisted implementation, the speed of encoding was a factor of between four and five faster than a software encoder running on the same CPU while allowing the CPU to perform other tasks during the encoding process.

With the development of Internet, more and more people believe that the future telecommunication network will be constructed based on IP technology. Session Initiation Protocol (SIP), which has advantages of simple entrainment method, good scalability and open protocols, is the main research topic on Voice-over-IP (VoIP). Although the client-server architecture currently used by SIP is simple and easy to maintain, it has limitation wherein service quality needs to rely on server performance. To improve this, the Internet Engineering Task Force (IETF) has created a draft to discuss the application of P2P (Peer-to-Peer) architecture in SIP, and we hope that the draft can help to provide good SIP service quality on P2P architecture, such as good fault tolerance and transmission performance. Our research is based on Chord architecture and aims to make P2P SIP architecture in an embedded User Agent. For the SIP internet telephone feature, we adjusts Chord algorithm to meet SIP internet telephone requirements. Furthermore, the adjustment to Chord makes it more applicable to the environment that users continuously join or leave, so that the revised Chord can be implemented with SIP protocol to achieve the P2P SIP goal.

There are many Operation Systems provide the interface likes the frame buffer in Linux. It let Application Programs can read and write the memory block tightly connecting the operating registers of display card directly to get the goal of directly modifying the monitor display. However, although we have the frame buffer, this kind of graphic processing method is not enough to provide a real-time graphic performance under the needed of huge block drawing and moving. In order to eliminate the drawback of the low graphic performance of using pure software, there are many cards with 3D graphic engine produced for speeding up the performance of 3D games, like ATI Radeon X850[1] , NVIDIA GeForce 6800[2] and so on. Although the embedded products like digital TV or mobile phone are not needed to have a complex and powerful 3D graphic engine, the idea of speeding up drafting can be provided for the embedded system as a reference. The graphic engine can not only provide a real-time performance of drafting, but also share the work of CPU in embedded system, to achieve the goal of improving graphic performance and cost down. In the paper, we will implement a 2D graphic engine dynamic shared library for combining the 2D graphic engine and frame buffer on the V/PB926EJ-S target board. To achieve the goal of improving graphic performance, come true the real-time graphic processing ability of Embedded LINUX. And providing a convenient, quickly and reliable software technique of combining hardware resource and operation system together based on the experiment.

OpenGL ES 2.0 is the newest 3D graphics technology for hand-held devices established by Khronos. Users need a shading language compiler and a graphics card which is supportive for OpenGL ES 2.0 to develop their application on OpenGL ES 2.0. Without a graphcis processing unit and a corresponding compiler, one can not develop a 3D graphics application based on OpenGL ES 2.0. In order to solve these problems, we proposed an emulator for OpenGL ES 2.0 based on C-language compiler. The proposed emulator applies C-language compiler and CPU to fulfill the specification of OpenGL ES 2.0. With the proposed emulator, application developers can develop a 3D graphics application for OpenGL ES 2.0 without a specific hardware and a corresponding compiler and hardware designers also can compare and debug when designing their own graphics processing unit.

With the improvement in VLSI technology, realization of multiple processor cores on a single chip becomes easier. Therefore, more and more users execute applications on current multi-core architectures. The multi-core system has a brilliant performance in executing multi-threaded applications, but this system could not gain any performance in single-threaded applications. This paper proposes a multi-core architecture for enhancing single-threaded performance in embedded system, and focuses on four points: 1. Construct a simple out-of-order execution core. 2. Design a dynamically scheduled instruction analyzer. 3. Design a mechanism for sharing operands between two cores. 4. Design a mechanism for committing instructions synchronously between two cores. The architecture of each core is single-issue out-of-order instruction pipe. First, instruction analyzer will fetch instructions and generate instruction dependence tags by detecting the dependencies among the fetched instructions, then schedule instructions dynamically and dispatch to the cores. In the core, instructions can know where to get required operands according to the information of instruction tags, this mechanism enables data can be shared between two cores. Instructions are executed by data-driven approach, but in-order complete to maintain the correctness of the program order. Based on ARM instruction set, this paper tries to explore ways to achieve interaction control mechanisms between two cores and to accelerate a single-thread in the dual-core architecture. We write a simulation model of the proposed architecture in C language as our trace-driven simulation framework and the MediaBench suite is selected for the experiments. According simulation result, the architecture can obtain average 40% performance speedup comparing to the five-stage pipelined architecture.

Roadway illumination is a vital component of safety while driving during the night. There are regulations in place to ensure all publicly maintained roads are properly lit, but the validation process is too time consuming, costly, and dangerous for adequate data collection studies. The work in this thesis is aimed toward remedying this problem by creating an Advanced Lighting Measurement System (ALMS) capable of recording illumination readings while traveling at normal driving speeds. This solution is based on the Arduino Uno development board, a cost effective yet powerful embedded platform. This thesis involves collecting data along 100 centerline miles of Florida roadways and converting the resulting illumination readings into GIS format, allowing them to be included in the roadway database of the Florida Department of Transportation (FDOT). By including this data FDOT will be able to repair poorly lit corridors and will be aware of possible safety concerns. The illumination values recorded by the ALMS have been validated and verified as an accurate replacement for conventional lighting measurement system.

MP3, or MPEG-1 Layer 3, is the most widely-used format for storing compressed audio. MP3 is more advantageous than uncompressed audio (PCM), offering a much smaller size but without a noticeable loss in audio quality. This report will demonstrate decoding and playback of MP3 audio using a TLL5000 FPGA board. / text

In order to maximize operating time of an industrial machine and minimize stand-by time, service time and operating costs, a diagnostic system can be a useful tool. Diagnostic systems employ information already available in a machine’s control system (such as control signals, system state, sensor readings and so forth) to perform intelligent fault detection and localisation, and predict future faults and service needs. CC Systems develops advanced electronics and control systems for industrial machines and vehicles operating in rough environments. One of their products is a diagnostic platform called Diagnostic Runtime Engine (DRE), supplying the customer with a tool for building a diagnostic system. The platform offers supervision of the control system. Actions are performed when it detects a possible fault or indication of a potential future fault. An action could be for example the creation of an alarm. The DRE, as designed today, only works together with a control system running in an environment called CoDeSys. In this master thesis a new architecture of the platform is presented, with the objective to make the platform compatible with an arbitrary control system. A prototype is implemented to prove the concept of the suggested architecture model. A number of different standard diagnostic blocks, used for building the diagnostic system, are also suggested with the objective to make it easier for the user to employ the DRE. A proposition of how development with the diagnostic platform can proceed beyond this thesis is also presented. / För att maximera drifttid hos en industriell maskin och minimera driftskostnader samt standby- och service-tid, kan ett diagnostiksystem användas. Ett sådant system använder sig av information som redan finns tillgänglig i maskinens styrsystem (så som styrsignaler, tillstånd, sensorvärden och så vidare) för att utföra feldetektering och fellokalisering samt analys av möjliga framtida feltillstånd och servicebehov. CC Systems utvecklar avancerade elektronikkomponenter och styrsystem för industriella maskiner och fordon. En av deras produkter är en diagnostikplattform, Diagnostic Runtime Engine (DRE), som erbjuder ett verktyg för att bygga upp ett diagnostiksystem. Plattformen möjliggör övervakning av styrsystemet, och detektion av ett nuvarande feltillstånd eller möjligt framtida feltillstånd leder till att en handling utförs. En handling kan till exempel vara att ett alarm skapas. Diagnostikplattformen, som den är gjord idag, fungerar bara tillsammans med ett styrsystem som är implementerat i utvecklingsmiljön CoDeSys. I detta examensarbete presenteras en ny arkitektur på plattformen som möjliggör användande tillsammans med ett godtyckligt styrsystem. En prototyp är implementerad för att visa att den föreslagna arkitekturmodellen fungerar i praktiken. Dessutom är ett antal standard-diagnostikblock, som används då ett diagnostiksystem byggs upp, föreslagna. Standardblocken har till syfte att underlätta användandet av diagnostikplattformen. Ett förslag för hur DRE kan byggas om och utvecklas i framtiden är också presenterat.

To make a camera more user friendly or let it operate without an user the camera objective needs to be able to put thecamera lens in focus. This functionality requires a motor of some sort, due to its many benefits the ultrasonic motor is apreferred choice. The motor requires a driving circuit to produce the appropriate signals and this is what this thesis is about.Themain difficulty that needs to be considered is the fact that the ultrasonic motor is highly non-linear.This paper will give a brief walk through of how the ultrasonic motor works,its pros and cons and how to control it. How thedriving circuit is designed and what role the various components fills. The regulator is implemented in C-code and runs on amicro processor while the actual signal generation is done on a CPLD. The report ends with a few suggestions of how toimprove the system should the presented solution not perform at a satisfactory level.