From the initial implementations for the DEC PDP-11 to those of today done for commodity PICs, the TCP/IP code stack continues to work its way into a smaller and more omnipresent class of devices. One shortcoming of current devices on the leading edge of this trend is that they belong more to the microcontroller categories, which typically lack any appreciable signal processing capability. Applications such as consumer electronics and wireless sensor networks could benefit greatly from single-chip network-capable devices which are based on a Digital Signal Processing (DSP) core rather than a microcontroller. This report details the design and implementation of a partial TCP/IP code stack intended for such a DSP. / text

O aumento da popularidade da Internet e a criação de novos meios de transmissão estimulam um explosivo crescimento da taxa de transmissão de dados sobre a Internet. Assim, o processamento TCP/IP baseado em software torna-se um gargalo por não processar os pacotes na velocidade das linhas de transmissão, em especial os pacotes da camada de transporte. Conseqüentemente, surge a necessidade de implementação em hardware do processamento TCP/IP, o que traria vantagens como aceleração do processamento do fluxo de dados. Neste sentido, este trabalho apresenta a arquitetura do iNetCore, descrita em VHDL, para processamento dos protocolos das camadas de rede e transporte em hardware. Duas implementações desta arquitetura foram elaboradas, buscando explorar o espaço de projeto e analisar os resultados obtidos na síntese para a tecnologia ASIC e FPGA, e o desempenho no processamento de pacotes. Uma arquitetura HW/SW contendo o iNetCore foi prototipada sobre a placa Virtex- II Pro Development System. Em conjunto com essa arquitetura, foi implementada uma interface de comunicação com o barramento OPB, tornando possível a implementação de softwares da camada de aplicação que queiram usar a pilha TCP/IP desenvolvida em hardware. Por fim, foram efetuados experimentos para avaliar o desempenho da arquitetura HW/SW no processamento de segmentos TCP. A arquitetura HW/SW em conjunto com o iNetCore alcançou um throughput de até 1,45 Gbps, possibilitando o uso da arquitetura para processamento de pacotes TCP/IP na plenitude de banda disponíveis em redes gigabit. / The advent of new transmission lines stimulates an explosive increase of the Internet data-transmission rate. Thus, the TCP/IP processing based on software became a bottleneck, because it cannot reach the transmission line speed required, specially in the transmission of transport layer packets. This limitation brings the necessity of implementation of the TCP/IP processing in hardware, what it would bring advantages in the acceleration of data flow processing. In this way, this work presents the iNetCore architecture, described in VHDL, able to process the transport and network layers protocols in hardware. Two implementations of this architecture were implemented. The objective is to explore the design space and to analyze the results in ASIC and FPGA technology synthesis. Also, a simulation environment was built to analyze the performance in the packets computation. A HW/SW architecture containing the iNetcore was prototyped on Virtex-II Pro Development System board. In conjunction with this architecture, it was implemented a communication interface with OPB bus, which makes possible the development of application layer softwares that may use the hardware TCP/IP stack developed. Finally, experiments were realized in order to evaluate the HW/SW architecture performance in the TCP segments processing. The HW/SW architecture together with the iNetCore reached a throughput of about 1.45 Gbps in the TCP/IP packets processing. It proves its potential to use available bandwidth in gigabit networks.

O aumento da popularidade da Internet e a criação de novos meios de transmissão estimulam um explosivo crescimento da taxa de transmissão de dados sobre a Internet. Assim, o processamento TCP/IP baseado em software torna-se um gargalo por não processar os pacotes na velocidade das linhas de transmissão, em especial os pacotes da camada de transporte. Conseqüentemente, surge a necessidade de implementação em hardware do processamento TCP/IP, o que traria vantagens como aceleração do processamento do fluxo de dados. Neste sentido, este trabalho apresenta a arquitetura do iNetCore, descrita em VHDL, para processamento dos protocolos das camadas de rede e transporte em hardware. Duas implementações desta arquitetura foram elaboradas, buscando explorar o espaço de projeto e analisar os resultados obtidos na síntese para a tecnologia ASIC e FPGA, e o desempenho no processamento de pacotes. Uma arquitetura HW/SW contendo o iNetCore foi prototipada sobre a placa Virtex- II Pro Development System. Em conjunto com essa arquitetura, foi implementada uma interface de comunicação com o barramento OPB, tornando possível a implementação de softwares da camada de aplicação que queiram usar a pilha TCP/IP desenvolvida em hardware. Por fim, foram efetuados experimentos para avaliar o desempenho da arquitetura HW/SW no processamento de segmentos TCP. A arquitetura HW/SW em conjunto com o iNetCore alcançou um throughput de até 1,45 Gbps, possibilitando o uso da arquitetura para processamento de pacotes TCP/IP na plenitude de banda disponíveis em redes gigabit. / The advent of new transmission lines stimulates an explosive increase of the Internet data-transmission rate. Thus, the TCP/IP processing based on software became a bottleneck, because it cannot reach the transmission line speed required, specially in the transmission of transport layer packets. This limitation brings the necessity of implementation of the TCP/IP processing in hardware, what it would bring advantages in the acceleration of data flow processing. In this way, this work presents the iNetCore architecture, described in VHDL, able to process the transport and network layers protocols in hardware. Two implementations of this architecture were implemented. The objective is to explore the design space and to analyze the results in ASIC and FPGA technology synthesis. Also, a simulation environment was built to analyze the performance in the packets computation. A HW/SW architecture containing the iNetcore was prototyped on Virtex-II Pro Development System board. In conjunction with this architecture, it was implemented a communication interface with OPB bus, which makes possible the development of application layer softwares that may use the hardware TCP/IP stack developed. Finally, experiments were realized in order to evaluate the HW/SW architecture performance in the TCP segments processing. The HW/SW architecture together with the iNetCore reached a throughput of about 1.45 Gbps in the TCP/IP packets processing. It proves its potential to use available bandwidth in gigabit networks.

O aumento da popularidade da Internet e a criação de novos meios de transmissão estimulam um explosivo crescimento da taxa de transmissão de dados sobre a Internet. Assim, o processamento TCP/IP baseado em software torna-se um gargalo por não processar os pacotes na velocidade das linhas de transmissão, em especial os pacotes da camada de transporte. Conseqüentemente, surge a necessidade de implementação em hardware do processamento TCP/IP, o que traria vantagens como aceleração do processamento do fluxo de dados. Neste sentido, este trabalho apresenta a arquitetura do iNetCore, descrita em VHDL, para processamento dos protocolos das camadas de rede e transporte em hardware. Duas implementações desta arquitetura foram elaboradas, buscando explorar o espaço de projeto e analisar os resultados obtidos na síntese para a tecnologia ASIC e FPGA, e o desempenho no processamento de pacotes. Uma arquitetura HW/SW contendo o iNetCore foi prototipada sobre a placa Virtex- II Pro Development System. Em conjunto com essa arquitetura, foi implementada uma interface de comunicação com o barramento OPB, tornando possível a implementação de softwares da camada de aplicação que queiram usar a pilha TCP/IP desenvolvida em hardware. Por fim, foram efetuados experimentos para avaliar o desempenho da arquitetura HW/SW no processamento de segmentos TCP. A arquitetura HW/SW em conjunto com o iNetCore alcançou um throughput de até 1,45 Gbps, possibilitando o uso da arquitetura para processamento de pacotes TCP/IP na plenitude de banda disponíveis em redes gigabit. / The advent of new transmission lines stimulates an explosive increase of the Internet data-transmission rate. Thus, the TCP/IP processing based on software became a bottleneck, because it cannot reach the transmission line speed required, specially in the transmission of transport layer packets. This limitation brings the necessity of implementation of the TCP/IP processing in hardware, what it would bring advantages in the acceleration of data flow processing. In this way, this work presents the iNetCore architecture, described in VHDL, able to process the transport and network layers protocols in hardware. Two implementations of this architecture were implemented. The objective is to explore the design space and to analyze the results in ASIC and FPGA technology synthesis. Also, a simulation environment was built to analyze the performance in the packets computation. A HW/SW architecture containing the iNetcore was prototyped on Virtex-II Pro Development System board. In conjunction with this architecture, it was implemented a communication interface with OPB bus, which makes possible the development of application layer softwares that may use the hardware TCP/IP stack developed. Finally, experiments were realized in order to evaluate the HW/SW architecture performance in the TCP segments processing. The HW/SW architecture together with the iNetCore reached a throughput of about 1.45 Gbps in the TCP/IP packets processing. It proves its potential to use available bandwidth in gigabit networks.

Sterners Specialfabrik AB tillverkar bland annat mynt- och biljettautomater. För att underlätta felsökning, underhåll, avläsning av statistik med mera på en automat är det lämpligt att detta utförs på en PC över Internet. Det innebär att automaten inte behöver besökas då dessa uppgifter skall utföras. Examensarbetet går ut på att få en PIC mikrokontroller att kommunicera med en användare vid en PC över internet. För detta krävs att en TCP/IP stack implementeras på PICmikrokontrollern. Arbetet ledde till en fungerande demoapplikation som klarar av att kommunicera över TCP/IP. Demoapplikationen innehåller diverse olika funktioner för att demonstrera hur en automat skulle kunna styras och övervakas.

Techn. University, Diss., 2004--Berlin.

No description available.

International Telemetering Conference Proceedings / October 20-23, 2003 / Riviera Hotel and Convention Center, Las Vegas, Nevada / The Western Aeronautical Test Range (WATR) operates the ground stations for research vehicles operating at the NASA Dryden Flight Research Center (DFRC). Recently, the WATR implemented a new system for distributing Time, Space, and Position Information (TSPI) data. The previous system for processing this data was built on archaic hardware that is no longer supported, running legacy software with no upgrade path. The purpose of the Radar Information Processing System (RIPS) is to provide the ability to acquire TSPI data from a variety of sources and process the data for subsequent distribution to other destinations located at the various DFRC facilities. RIPS is built of commercial, off the shelf (COTS) hardware installed in Personal Computers (PC). Data is transported between these computers on a Gigabit Ethernet network. The software was developed using C++ with a modular, object-oriented design approach.

Yuen Ka-nang. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2001. / Includes bibliographical references (leaves 133-135). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iii / Chapter 1. --- INTRODUCTION --- p.1 / Chapter 1.1. --- Background --- p.1 / Chapter 1.2. --- Objectives --- p.1 / Chapter 1.3. --- Overview of Thesis --- p.2 / Chapter 2. --- NETWORK ASPECT OF THE VOIP TECHNOLOGY --- p.3 / Chapter 2.1. --- VoIP Overview --- p.3 / Chapter 2.2. --- Elements in VoIP --- p.3 / Chapter 2.2.1. --- Call Setup --- p.3 / Chapter 2.2.2. --- Media Capture/Playback --- p.4 / Chapter 2.2.3. --- Media Encoding/Decoding --- p.4 / Chapter 2.2.4. --- Media Transportation --- p.5 / Chapter 2.3. --- Performance Factors Affecting VoIP --- p.6 / Chapter 2.3.1. --- Network Bandwidth --- p.6 / Chapter 2.3.2. --- Latency --- p.6 / Chapter 2.3.3. --- Packet Loss --- p.7 / Chapter 2.3.4. --- Voice Quality --- p.7 / Chapter 2.3.5. --- Quality of Service (QoS) --- p.7 / Chapter 2.4. --- Different Requirements of Intranet VoIP and Internet VoIP --- p.8 / Chapter 2.4.1. --- Packet Loss/Delay/Jitter --- p.8 / Chapter 2.4.2. --- Interoperability --- p.9 / Chapter 2.4.3. --- Available Bandwidth --- p.9 / Chapter 2.4.4. --- Security Requirement --- p.10 / Chapter 2.5. --- Some Feasibility Investigations --- p.10 / Chapter 2.5.1. --- Bandwidth Calculation --- p.10 / Chapter 2.5.2. --- Simulation --- p.12 / Chapter 2.5.3. --- Conclusion --- p.17 / Chapter 2.5.4. --- Simulation Restrictions --- p.17 / Chapter 3. --- SOFTWARE ASPECT OF THE VOIP TECHNOLOGY --- p.19 / Chapter 3.1. --- VoIP Client in JMF --- p.19 / Chapter 3.1.1. --- Architecture --- p.20 / Chapter 3.1.2. --- Incoming Voice Stream Handling --- p.23 / Chapter 3.1.3. --- Outgoing Voice Stream Handling --- p.23 / Chapter 3.1.4. --- Relation between Incoming/Outgoing Voice Stream Handling --- p.23 / Chapter 3.1.5. --- Areas for Further Improvement --- p.25 / Chapter 3.2. --- Capture/Playback Enhanced VoIP Client --- p.26 / Chapter 3.2.1. --- Architecture --- p.27 / Chapter 3.2.2. --- Native Voice Playback Mechanism --- p.29 / Chapter 3.2.3. --- Native Voice Capturing Mechanism --- p.31 / Chapter 3.3. --- Win32 C++ VoIP Client --- p.31 / Chapter 3.3.1. --- Objectives --- p.32 / Chapter 3.3.2. --- Architecture --- p.33 / Chapter 3.3.3. --- Problems and Solutions in Implementation --- p.37 / Chapter 3.4. --- Win32 DirectSound C++ VoIP Client --- p.38 / Chapter 3.4.1. --- Architecture --- p.39 / Chapter 3.4.2. --- DirectSound Voice Playback Mechanism --- p.40 / Chapter 3.4.3. --- DirectSound Voice Capturing Mechanism --- p.44 / Chapter 3.5. --- Testing VoIP Clients --- p.45 / Chapter 3.5.1. --- Setup of Experiment --- p.45 / Chapter 3.5.2. --- Experiment Results --- p.47 / Chapter 3.5.3. --- Experiment Conclusion --- p.48 / Chapter 3.6. --- Real-time Voice Stream Mixing Server --- p.48 / Chapter 3.6.1. --- Structure Overview --- p.48 / Chapter 3.6.2. --- Experiment --- p.53 / Chapter 3.6.3. --- Conclusion --- p.54 / Chapter 4. --- EXPERIMENTAL STUDIES --- p.55 / Chapter 4.1. --- Pure IP-side VoIP-based Call Center ´ؤ VoIP in Education --- p.55 / Chapter 4.1.1. --- Architecture --- p.55 / Chapter 4.1.2. --- Client Structure --- p.56 / Chapter 4.1.3. --- Client Applet User Interface --- p.58 / Chapter 4.1.4. --- Observations --- p.63 / Chapter 4.2. --- A Simple PBX Experiment --- p.63 / Chapter 4.2.1. --- Structural Overview --- p.63 / Chapter 4.2.2. --- PSTN Gateway Server Program --- p.64 / Chapter 4.2.3. --- Problems and Solutions in Implementation --- p.66 / Chapter 4.2.4. --- Experiment 1 --- p.66 / Chapter 4.2.5. --- Experiment 2 --- p.68 / Chapter 5. --- A COMPREHENSIVE VOIP PROJECT 一 GRADUATE SECOND PHONE (GSP) --- p.72 / Chapter 5.1. --- Overview --- p.72 / Chapter 5.1.1. --- Background --- p.72 / Chapter 5.1.2. --- Architecture --- p.76 / Chapter 5.1.3. --- Technologies Used --- p.78 / Chapter 5.1.4. --- Major Functions --- p.80 / Chapter 5.2. --- Client --- p.84 / Chapter 5.2.1. --- Structure Overview --- p.85 / Chapter 5.2.2. --- Connection Procedure --- p.89 / Chapter 5.2.3. --- User Interface --- p.91 / Chapter 5.2.4. --- Observations --- p.92 / Chapter 5.3. --- Gateway --- p.94 / Chapter 5.3.1. --- Structure Overview --- p.94 / Chapter 5.3.2. --- Connection Procedure --- p.97 / Chapter 5.3.3. --- Caller ID Simulator --- p.97 / Chapter 5.3.4. --- Observations --- p.98 / Chapter 5.4. --- Server --- p.101 / Chapter 5.4.1. --- Structure Overview --- p.101 / Chapter 5.5. --- Details of Major Functions --- p.103 / Chapter 5.5.1. --- Secure Local Voice Message Box --- p.104 / Chapter 5.5.2. --- Call Distribution --- p.106 / Chapter 5.5.3. --- Call Forward --- p.112 / Chapter 5.5.4. --- Call Transfer --- p.115 / Chapter 5.6. --- Experiments --- p.116 / Chapter 5.6.1. --- Secure Local Voice Message Box --- p.117 / Chapter 5.6.2. --- Call Distribution --- p.118 / Chapter 5.6.3. --- Call Forward --- p.121 / Chapter 5.6.4. --- Call Transfer --- p.122 / Chapter 5.6.5. --- Dial Out --- p.124 / Chapter 5.7. --- Observations --- p.125 / Chapter 5.8. --- Outlook --- p.126 / Chapter 5.9. --- Alternatives --- p.127 / Chapter 5.9.1. --- Netmeeting --- p.127 / Chapter 5.9.2. --- OpenH323 --- p.128 / Chapter 6. --- CONCLUSIONS --- p.129 / Bibliography --- p.133

Tese de mestr.. Engenharia Electrotécnica e de Computadores. Faculdade de Engenharia. Universidade do Porto. 1998