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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

A Design Study of an Arithmetic Unit for Finite Fields / En Designstudie av en Aritmetisk Enhet för Ändliga Kroppar

Tångring, Ivar January 2003 (has links)
<p>This thesis investigates how systolic architectures can be used in the implementation of an arithmetic unit for small finite fields of characteristic two with polynomial basis representation. </p><p>Systolic architectures provide very high performance but also consume a lot of chip area. A number of design methods for tailoring the systolic arrays for a specified requirement are presented, making it possible to trade throughput, chip area and propagation delays for oneanother. </p><p>A study is also made on how these systolic arrays can be combined to form an arithmetic logic unit, ALU, that canperform operations in many different fields. A number of design alternatives are presented, and an example ALU is presented to give an idea of the performance of such a circuit.</p>
2

A Design Study of an Arithmetic Unit for Finite Fields / En Designstudie av en Aritmetisk Enhet för Ändliga Kroppar

Tångring, Ivar January 2003 (has links)
This thesis investigates how systolic architectures can be used in the implementation of an arithmetic unit for small finite fields of characteristic two with polynomial basis representation. Systolic architectures provide very high performance but also consume a lot of chip area. A number of design methods for tailoring the systolic arrays for a specified requirement are presented, making it possible to trade throughput, chip area and propagation delays for oneanother. A study is also made on how these systolic arrays can be combined to form an arithmetic logic unit, ALU, that canperform operations in many different fields. A number of design alternatives are presented, and an example ALU is presented to give an idea of the performance of such a circuit.
3

Tensor Rank

Erdtman, Elias, Jönsson, Carl January 2012 (has links)
This master's thesis addresses numerical methods of computing the typical ranks of tensors over the real numbers and explores some properties of tensors over finite fields. We present three numerical methods to compute typical tensor rank. Two of these have already been published and can be used to calculate the lowest typical ranks of tensors and an approximate percentage of how many tensors have the lowest typical ranks (for some tensor formats), respectively. The third method was developed by the authors with the intent to be able to discern if there is more than one typical rank. Some results from the method are presented but are inconclusive. In the area of tensors over nite filds some new results are shown, namely that there are eight GLq(2) GLq(2) GLq(2)-orbits of 2 2 2 tensors over any finite field and that some tensors over Fq have lower rank when considered as tensors over Fq2 . Furthermore, it is shown that some symmetric tensors over F2 do not have a symmetric rank and that there are tensors over some other finite fields which have a larger symmetric rank than rank.

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