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The Global ETD Search service is a free service for researchers
to find electronic theses and dissertations. This service is
provided by the
Networked Digital Library of Theses and Dissertations.
Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
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Showing 1 to 2 of 2 (0.064 seconds)Spelling suggestions: "subject:"aritmetiska enhet"" "subject:"aritmetik enhet""
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A Design Study of an Arithmetic Unit for Finite Fields / En Designstudie av en Aritmetisk Enhet för Ändliga KropparTångring, Ivar January 2003 (has links)
<p>This thesis investigates how systolic architectures can be used in the implementation of an arithmetic unit for small finite fields of characteristic two with polynomial basis representation. </p><p>Systolic architectures provide very high performance but also consume a lot of chip area. A number of design methods for tailoring the systolic arrays for a specified requirement are presented, making it possible to trade throughput, chip area and propagation delays for oneanother. </p><p>A study is also made on how these systolic arrays can be combined to form an arithmetic logic unit, ALU, that canperform operations in many different fields. A number of design alternatives are presented, and an example ALU is presented to give an idea of the performance of such a circuit.</p>
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A Design Study of an Arithmetic Unit for Finite Fields / En Designstudie av en Aritmetisk Enhet för Ändliga KropparTångring, Ivar January 2003 (has links)
This thesis investigates how systolic architectures can be used in the implementation of an arithmetic unit for small finite fields of characteristic two with polynomial basis representation. Systolic architectures provide very high performance but also consume a lot of chip area. A number of design methods for tailoring the systolic arrays for a specified requirement are presented, making it possible to trade throughput, chip area and propagation delays for oneanother. A study is also made on how these systolic arrays can be combined to form an arithmetic logic unit, ALU, that canperform operations in many different fields. A number of design alternatives are presented, and an example ALU is presented to give an idea of the performance of such a circuit.
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