The grain-size dependences of thermal conductivity and electrical resistivity of polycrystalline and nanocrystalline nickel were measured by the flash method and four-point probe method, respectively. Nanocrystalline nickel was made by the pulsed-current electrodeposition process, while polycrystalline nickel was commercially available Ni 200 in annealed condition. The grain sizes of the materials examined ranged from 28 nanometers to 57 micrometers. Noticeable changes in thermal conductivity and electrical resistivity with grain size were observed in particular for samples with grain sizes less than 100 nm. These results can be explained on the basis of the rapid increase in the intercrystalline grain boundary and triple junction volume fractions at very small grain sizes. The relationship between thermal conductivity and electrical resistivity of nanocrystalline nickel follows the classic Wiedemann-Franz law.

Nano-grained nickel produced by electroforming technique was investigated for its microstructure evolution and mechanical properties upon annealing. It was found that during low temperature annealing (T<250 oC), electroformed nano-grained nickel showed scattered and isolated abnormal grain growth, followed by a major abnormal grain growth at 320 oC. A secondary abnormal grain growth, featuring faceted grain boundaries, was observed at a higher annealing temperature (T=528 oC). A semi-in-situ observation using optical microscopy was conducted to track the movement of the faceted grain boundaries, and it was found that these boundaries were mostly immobile. The mechanical properties under various annealing conditions were studies using hardness and tensile testing. The hardness was observed to decrease with increasing annealing temperature. The material became very brittle after annealing at 320 oC or higher temperatures. Fractography investigation showed that the brittleness is caused by intergranular fracture.

The grain-size dependences of thermal conductivity and electrical resistivity of polycrystalline and nanocrystalline nickel were measured by the flash method and four-point probe method, respectively. Nanocrystalline nickel was made by the pulsed-current electrodeposition process, while polycrystalline nickel was commercially available Ni 200 in annealed condition. The grain sizes of the materials examined ranged from 28 nanometers to 57 micrometers. Noticeable changes in thermal conductivity and electrical resistivity with grain size were observed in particular for samples with grain sizes less than 100 nm. These results can be explained on the basis of the rapid increase in the intercrystalline grain boundary and triple junction volume fractions at very small grain sizes. The relationship between thermal conductivity and electrical resistivity of nanocrystalline nickel follows the classic Wiedemann-Franz law.

Hydrogenated amorphous silicon (a-Si:H) thin film transistor (TFT) has been used in active matrix liquid crystal displays (LCDs) and medical x-ray imagers, in which the TFT acts as pixel switches. However, instability of a-Si:H TFT is a major issue in applications where TFTs are also required to function as analogue circuit elements, such as in emerging organic light emitting diode (OLED) displays. It is known that a-Si:H TFT shows drain current degradation under electrical operation, due to two instability mechanisms: (i) defect creation in the a-Si:H active layer, and (ii) charge trapping in the gate dielectric. Nanocrystalline silicon (nc-Si) TFT has been proposed as a high performance alternative. Therefore, this thesis focuses on the design of nc-Si TFT and its outstanding issues, in the industry standard bottom-gate structure. The key for obtaining a stable TFT lies in developing a highly crystalline nc-Si active layer, without the so-called amorphous incubation layer. Therefore, processing of nc-Si by plasma enhanced chemical vapor deposition (PECVD) is studied and PECVD parameters are optimized. It is shown that very thin (15 nm) layers with crystallinity of around 60% can be obtained. Moreover, it is possible to eliminate the amorphous incubation layer, as transmission electron microscope (TEM) images showed that crystalline grains start growing immediately upon deposition at the gate dielectric interface. The nc-Si TFT reported in this work advances the state-of-the-art, by demonstrating that defect state creation is absent in the nc-Si active layer, which is deduced by performing several characterization techniques. In addition, with the proper design of the nitride gate dielectric, i.e. by using a nitrogen-rich nitride, the charge trapping instability can be minimized. Thus, it is shown that the nc-Si TFT is much more stable than the a-Si:H counterpart. Another issue with nc-Si TFT is its high drain leakage current, i.e. off-current. It is shown that off-current is determined by the conductivity of nc-Si active layer, and also affected by the quality of the silicon/passivation nitride interface. The off-current can be minimized by using a bi-layer structure so that a thin (15 nm) nc-Si is capped with a thin (35nm) a-Si:H, and values as low as 0.1 pA can be obtained. The low off-current along with superior stability of nc-Si TFT, coupled with its fabrication in the industry standard 13.56 MHz PECVD system, make it very attractive for large area applications such as pixel drivers in active matrix OLED displays and x-ray imagers.

Thin film transistors (TFTs), the heart of highly functional and ultra-compact active-matrix (AM) backplanes, have driven explosive growth in both the variety and utility of large-area electronics over the past few decades. Nanocrystalline silicon (nc-Si:H) TFTs have recently attracted attention as a high-performance and low-cost alternative to existing amorphous silicon (a-Si:H) and polycrystalline silicon (poly-Si) TFTs, in that they have the strong potentials which a-Si:H (low carrier mobility and poor device stability) and poly-Si (poor device uniformity and high manufacturing cost) counterparts do not have. However, the current nc-Si:H TFTs expose several challenging material and devices issues, on which the dissertation focuses. In our material study, the growth of gate-quality SiO2 films and highly conductive nc-Si:H contacts based on conventional plasma-enhanced chemical vapor deposition (PECVD) is systematically investigated, which can lead to high performance, reproducibility, predictability, and stability in the nc-Si:H TFTs. Particularly to overcome a low field effect mobility in the p-channel transistors, the possibility of B(CH3)3 as an alternative dopant source to current B2H6 is examined. The resultant p-doped nc-Si:H contacts demonstrate comparable performance to the state of the art with the maximum dark conductivity of 1.11 S/cm over 70% film crystallinity. Based on the highest-quality SiO2 and nc-Si:H contacts developed, complementary (n- and p-channel) top-gate nc-Si:H TFTs with a staggered source/drain geometry are designed, fabricated, and characterized. The n-channel TFTs demonstrate a threshold voltage VTn of 6.4 V, a field effect mobility of electrons μn of 15.54 cm2/Vs, a subthreshold slope S of 0.67 V/decade, and an on/off current ratio Ion/Ioff of 10^5, while the corresponding p-channel TFTs exhibit VTp of -26.2 V, μp of 0.24 cm2/Vs, S of 4.72 V/ decade, and Ion/Ioff of 10^4. However, the TFTs show significant non-ideal behaviors that considerably limit device performance: high leakage current in the off-state, transconductance degradation under high gate bias, and threshold voltage instability in time. Quantitative insight into each non-ideality is provided in this research. Our study on the off-state conduction in the nc-Si:H TFTs reveals that the responsible mechanism for high leakage current, particularly at a high bias regime, is largely due to Poole-Frenkel emission of trapped carriers in the reverse-biased drain depletion region. This could be effectively suppressed by proposed offset-gated structure without compromising the on-state performance. A numerical analysis of the transconductance degradation shows that the parasitic resistance components that are present in the nc-Si:H TFTs strongly degrade transconductance and thus a field effect mobility. Correspondingly, strategies for reduction in parasitic resistance of the TFT are presented. Lastly, the threshold voltage shift in the nc-Si:H TFT is attributed to the flatband voltage shift, which is mainly due to charge trapping in the PECVD SiO2 gate dielectric. Material and device study, and physical insight into non-ideal behaviors in the top-gate nc-Si:H TFTs reported in the dissertation constitute an arguably important step towards monolithic integration of pixels and peripheral driving circuits on a versatile active-matrix TFT backplane for high-performance and low-cost large-area electronics. However, the gate dielectric and the highly doped nc-Si:H contacts, still imposing considerable challenges, may require entirely new approaches.

Hydrogenated amorphous silicon (a-Si:H) thin film transistor (TFT) has been used in active matrix liquid crystal displays (LCDs) and medical x-ray imagers, in which the TFT acts as pixel switches. However, instability of a-Si:H TFT is a major issue in applications where TFTs are also required to function as analogue circuit elements, such as in emerging organic light emitting diode (OLED) displays. It is known that a-Si:H TFT shows drain current degradation under electrical operation, due to two instability mechanisms: (i) defect creation in the a-Si:H active layer, and (ii) charge trapping in the gate dielectric. Nanocrystalline silicon (nc-Si) TFT has been proposed as a high performance alternative. Therefore, this thesis focuses on the design of nc-Si TFT and its outstanding issues, in the industry standard bottom-gate structure. The key for obtaining a stable TFT lies in developing a highly crystalline nc-Si active layer, without the so-called amorphous incubation layer. Therefore, processing of nc-Si by plasma enhanced chemical vapor deposition (PECVD) is studied and PECVD parameters are optimized. It is shown that very thin (15 nm) layers with crystallinity of around 60% can be obtained. Moreover, it is possible to eliminate the amorphous incubation layer, as transmission electron microscope (TEM) images showed that crystalline grains start growing immediately upon deposition at the gate dielectric interface. The nc-Si TFT reported in this work advances the state-of-the-art, by demonstrating that defect state creation is absent in the nc-Si active layer, which is deduced by performing several characterization techniques. In addition, with the proper design of the nitride gate dielectric, i.e. by using a nitrogen-rich nitride, the charge trapping instability can be minimized. Thus, it is shown that the nc-Si TFT is much more stable than the a-Si:H counterpart. Another issue with nc-Si TFT is its high drain leakage current, i.e. off-current. It is shown that off-current is determined by the conductivity of nc-Si active layer, and also affected by the quality of the silicon/passivation nitride interface. The off-current can be minimized by using a bi-layer structure so that a thin (15 nm) nc-Si is capped with a thin (35nm) a-Si:H, and values as low as 0.1 pA can be obtained. The low off-current along with superior stability of nc-Si TFT, coupled with its fabrication in the industry standard 13.56 MHz PECVD system, make it very attractive for large area applications such as pixel drivers in active matrix OLED displays and x-ray imagers.

Thin film transistors (TFTs), the heart of highly functional and ultra-compact active-matrix (AM) backplanes, have driven explosive growth in both the variety and utility of large-area electronics over the past few decades. Nanocrystalline silicon (nc-Si:H) TFTs have recently attracted attention as a high-performance and low-cost alternative to existing amorphous silicon (a-Si:H) and polycrystalline silicon (poly-Si) TFTs, in that they have the strong potentials which a-Si:H (low carrier mobility and poor device stability) and poly-Si (poor device uniformity and high manufacturing cost) counterparts do not have. However, the current nc-Si:H TFTs expose several challenging material and devices issues, on which the dissertation focuses. In our material study, the growth of gate-quality SiO2 films and highly conductive nc-Si:H contacts based on conventional plasma-enhanced chemical vapor deposition (PECVD) is systematically investigated, which can lead to high performance, reproducibility, predictability, and stability in the nc-Si:H TFTs. Particularly to overcome a low field effect mobility in the p-channel transistors, the possibility of B(CH3)3 as an alternative dopant source to current B2H6 is examined. The resultant p-doped nc-Si:H contacts demonstrate comparable performance to the state of the art with the maximum dark conductivity of 1.11 S/cm over 70% film crystallinity. Based on the highest-quality SiO2 and nc-Si:H contacts developed, complementary (n- and p-channel) top-gate nc-Si:H TFTs with a staggered source/drain geometry are designed, fabricated, and characterized. The n-channel TFTs demonstrate a threshold voltage VTn of 6.4 V, a field effect mobility of electrons μn of 15.54 cm2/Vs, a subthreshold slope S of 0.67 V/decade, and an on/off current ratio Ion/Ioff of 10^5, while the corresponding p-channel TFTs exhibit VTp of -26.2 V, μp of 0.24 cm2/Vs, S of 4.72 V/ decade, and Ion/Ioff of 10^4. However, the TFTs show significant non-ideal behaviors that considerably limit device performance: high leakage current in the off-state, transconductance degradation under high gate bias, and threshold voltage instability in time. Quantitative insight into each non-ideality is provided in this research. Our study on the off-state conduction in the nc-Si:H TFTs reveals that the responsible mechanism for high leakage current, particularly at a high bias regime, is largely due to Poole-Frenkel emission of trapped carriers in the reverse-biased drain depletion region. This could be effectively suppressed by proposed offset-gated structure without compromising the on-state performance. A numerical analysis of the transconductance degradation shows that the parasitic resistance components that are present in the nc-Si:H TFTs strongly degrade transconductance and thus a field effect mobility. Correspondingly, strategies for reduction in parasitic resistance of the TFT are presented. Lastly, the threshold voltage shift in the nc-Si:H TFT is attributed to the flatband voltage shift, which is mainly due to charge trapping in the PECVD SiO2 gate dielectric. Material and device study, and physical insight into non-ideal behaviors in the top-gate nc-Si:H TFTs reported in the dissertation constitute an arguably important step towards monolithic integration of pixels and peripheral driving circuits on a versatile active-matrix TFT backplane for high-performance and low-cost large-area electronics. However, the gate dielectric and the highly doped nc-Si:H contacts, still imposing considerable challenges, may require entirely new approaches.

Nanocrystalline materials are being explored as potential off-chip interconnects materials for next generation microelectronics packaging. Mechanical behavior and deformation mechanisms in nanocrystalline copper and nickel have been explored. Nanostructured copper interconnections exhibit better fatigue life as compared to microcrystalline copper interconnects at a pitch of 100 and #956;m and lower. Nanocrystalline copper is quite stable upto 100 oC whereas nickel is stable even up to 400 oC. Grain boundary (GB) diffusion along with grain rotation and coalescence has been identified as the grain growth mechanism. Ultimate tensile and yield strength of nanocrystalline (nc) Cu and Ni are atleast 5 times higher than microcrystalline counterparts. Considerable amount of plastic deformation has been observed and the fracture is ductile in nature. Fracture surfaces show dimples much larger than grain size and stretching between dimples indicates localized plastic deformation. Activation energies for creep are close to GB diffusion activation energies indicating GB diffusion creep. Creep rupture at 45o to the loading axis and fracture surface shows lot of voiding and ductile kind of fracture. Grain rotation and coalescence along direction of maximum resolved shear stress plays an important role during creep. Grain refinement enhances the endurance limit and hence high cycle fatigue life. However, a deteriorating effect of grain refinement has been observed on low cycle fatigue life. This is because of the ease of crack initiation in nanomaterials. Persistent slip bands (PSBs) at an angle of 45o to loading axis are observed at higher strain ranges (> 1% for nc- Cu) with a width of about 50 nm. No relationship has been observed between PSBs and crack initiation. A non-recrystallization annealing treatment, 100 oC/ 2 hrs for nc- Cu and 250 oC/ 2 hrs for nc- Ni has been shown to improve the LCF life without lowering the strength much. Fatigue crack growth resistance is higher in nc- Cu and Ni compared to their microcrystalline counterparts. This is due to crack deflection at GBs leading to a tortuous crack path. Nanomaterials exhibit higher threshold stress intensity factors and effective threshold stress intensity is proportional to the elastic modulus of the material.

Nanoindentation has been widely used for measuring mechanical behavior of nanocrystalline (nc) metals that cannot be measured by tensile and compressive test. The hardness and elastic modulus are usually obtained by Oliver and Pharr method. However, this may not be true for materials showing viscoelastic characteristics. This study aims at clarifying the effect of testing parameters, especially loading rate and holding time, on the hardness and elastic modulus of a nanocrystalline Fe-51Ni coating obtained in nanoindentation tests as the material exhibits anelastic and creep characteristics. An analytical method based on the correspondence principle for linear viscoelasticity was developed. The holding displacement-time data obtained in indentation creep tests at a high loading rate of 20 mN/s were analyzed and material parameters related to the elastic, anelastic and creep characteristic were derived using a model containing one Maxwell unit and two Kelvin units. The anelastic deformation thus contains at least two relaxation processes having relaxation times of 0.37 s and 6.8 s, respectively and the creep deformation is described by a viscosity value of 4.2x104 GPa.s for the alloy in an as-deposited state. Moreover, electrodeposited (ED) Ni was analyzed by electron backscatter diffraction. Results indicated that the ED Ni exhibits a bimodal distribution of grain size. The grains having sizes larger than 2 £gm shows a strong fiber texture of <100>//ND, whereas the small grains (<2 £gm) are mainly randomly oriented.

<p>The structural quality of material (concentration and nature of defects) and optical properties (intensity and spectral emission range) of semiconductor materials are usually closely correlated. The idea of this work was to carry out a basic characterization of the structural (by X-ray diffraction technique and scanning electron microscopy) and optical (by micro photoluminescence measurements) properties of nanocrystalline ZnO samples and find a correlation. A number of ZnO samples prepared by atmospheric pressure metalorganic chemical vapor deposition at different regimes and on different substrates were investigated. According to the aim of the work the most important results can be summarized as following. The analysis of ZnO nanocrystalline structures deposited on Si (100) substrates have displayed a dependence of structural quality, morphology and microstructure as well as the optical spectral purity on the deposition temperature. The deposition at 500 ºС resulted in the massive of 1D ZnO nanopillars that demonstrated the best optical properties: a mono-emission in the ultraviolet spectral range was observed. Moreover, the results of microstructure investigation give a suggestion to the explanation of the ZnO nanopillars growth. The results obtained from ZnO on sapphire substrates revealed a moderate influence of the oxygen content during deposition on the structural quality of zinc oxide. However, a strong correlation between the oxygen content and deep-level emission intensity from ZnO nanostructures has been observed, which confirms the determinative role of oxygen for the defect emission from ZnO. It was shown that during the deposition of ZnO on specially prepared homoepitaxial template the substrate surface has not the major effect on the morphology of depositing ZnO structures. SiC was revealed to be the most appropriate substrate for hetero-deposition of textured ZnO nanostructures: the growth results in the massive of epitaxially related ZnO hexagons on the SiC (0001) plane. A number of factors - p-type conductivity of the substrate used, regular and uniform epitaxial growth of ZnO nanostructure, their excellent mono-spectral emission in short wavelength range of spectra, provides a strong background for further investigation of the electroluminescence properties of the obtained heterostructures and are of great importance for the progress of optoelectronics towards low-scaled elements.</p>