Over the past decade, the processing speed requirement of embedded systems has steadily increased. Since faster clocking of a single processor can no longer be considered to increase the processing speed of the system (due to overheating and other constraints), the development of multiprocessors on a single chip has stepped up to meet the demand. One approach has been to design and develop a multiprocessing platform to handle a large set of homogeneous applications. However, this development has been slow due to the intractable design space, which results when both the hardware and software are required to be adjustable to meet the needs of the dissimilar applications. A different approach has been to limit the number of targeted applications to be similar in some sense. By limiting the number of targeted applications to a cohesive set, the design space can become manageable. This thesis proposes a framework for a multiprocessing system-on-chip (MPSoC), consisting of a cohesive hardware and software architecture intended specifically for problems that are stream-oriented (e.g., video streaming). The framework allows the hardware and software to be customized to fit a specific application within the cohesive set, while narrowing the design space to a manageable set of design parameters. In addition, this thesis designs and develops an analytic model, using a discrete-time Markov chain, to measure the performance of an MPSoC framework implementation when the number of concurrent processing elements is varied. Finally, a chaotic simulated annealing algorithm was developed to determine an optimal mapping and scheduling of tasks to processing elements within the MPSoC.

Lab‐On‐a‐Chip (LOC) or Micro Total Analysis System (μTAS) technology requires precise control of minute amounts of liquid. Moving liquids in small capillaries requires bulky expensive external pumps that defy the purpose of microfabrication. By integrating a micropump into the device, it allows the system to be transportable, reliable, energy efficient and inexpensive. Such a microsystem built on a chip has been designed to study separation by dielectrophoretic chromatography. Nanobeads were successfully separated and used separately to measure fluid velocity and study the electroosmosis effect. Cell or beads of different type can be trapped in this system. This system encompasses a solid‐state AC electroosmotic pump for the manipulation of liquid‐containing cells or molecules. AC Electroosmosis is the movement of induced charges over polarised electrodes created by a non‐uniform electric field. The charges undergo Coulomb forces and drag the fluid with their motion. This results in bulk flow over the electrodes. This micro pump is used in a LOC by fabricating the pump on two sides of a microfluidic channel. The transport of material from what can be an analyte to a cell is of critical interest. The described system in the second part of this thesis presents the advantage of having a defined number of droplets, each of which is a lab on chip. The paradigm is the droplet and therefore the vessel that carries the information. Surfaces are then the place of interaction with the vessel which carries the second aspect of this thesis. Several approaches have been investigated, in particular by enclosing the droplet between two slides in order to increase the change of contact angle under the presence of polarised electrodes. This system is known as EWOD (ElectroWetting On Dielectric). It follows the approach of modified Lippmann laws and the modification of the apparent contact angle and therefore the motion of the droplet. The lid is somewhat a problem and the possibility of using liquid dielectrophoresis to create a multitude of droplets of calibrated volume is an advantage, as it is harder to create fixed‐volume droplets with an open geometry by EWOD due to contact angle hysteresis.

To harness the wealth of success and computational power from the microelectronics industry, lab-on-a-chip (LOAC) applications should be fully integrated with silicon platforms. This works demonstrates a dielectrophoresis-based LOAC device built entirely on silicon using standard CMOS (complementary metal oxide semiconductor) processing techniques. The signal phases on multiple electrodes were controlled with only four electrical contacts, which connected to the device using three metal layers separated with interlayer dielectric. Indium tin oxide was deposited on a milled plastic lid to provide the conductivity and optical clarity necessary to electrically actuate the particles and observe them. The particles and medium were in the microfluidic chamber formed by using conductive glue to bond the plastic milled lid to the patterned silicon substrate. A correlation between the particle velocities and the electric field gradients was made using video microscopy and COMSOL Multiphysics ® simulations.

Over the past decade, the processing speed requirement of embedded systems has steadily increased. Since faster clocking of a single processor can no longer be considered to increase the processing speed of the system (due to overheating and other constraints), the development of multiprocessors on a single chip has stepped up to meet the demand. One approach has been to design and develop a multiprocessing platform to handle a large set of homogeneous applications. However, this development has been slow due to the intractable design space, which results when both the hardware and software are required to be adjustable to meet the needs of the dissimilar applications. A different approach has been to limit the number of targeted applications to be similar in some sense. By limiting the number of targeted applications to a cohesive set, the design space can become manageable. This thesis proposes a framework for a multiprocessing system-on-chip (MPSoC), consisting of a cohesive hardware and software architecture intended specifically for problems that are stream-oriented (e.g., video streaming). The framework allows the hardware and software to be customized to fit a specific application within the cohesive set, while narrowing the design space to a manageable set of design parameters. In addition, this thesis designs and develops an analytic model, using a discrete-time Markov chain, to measure the performance of an MPSoC framework implementation when the number of concurrent processing elements is varied. Finally, a chaotic simulated annealing algorithm was developed to determine an optimal mapping and scheduling of tasks to processing elements within the MPSoC.

As VLSI fabrication technology scales, an increasing number of processing elements (cores) on a chip makes on-chip communication a new performance bottleneck. The Network-on-Chip (NoC) paradigm has emerged as an efficient and scalable infrastructure to handle the communication needs for such multi-core systems. In most existing NoCs, design decisions are made assuming that the NoC operates at the same or lower clock speed as the cores, which slows down the communication system. A major challenge in designing a high speed NoC is the difficulty of distributing a high speed, low power clock across the chip. In this dissertation, we first propose several techniques to address the issue of distributing a high-speed, low power, low jitter clock across the IC. We primarily focus our attention on resonant standing wave oscillators (SWOs), which have recently emerged as a promising technique for high-speed, low power clock generation. In addition, we also present a dynamic programming based approach to synthesize a low jitter, low power buffered H-tree for clock distribution. In the second part of this dissertation, we use these efficient clock distribution schemes to present a novel fast NoC design that relies on source synchronous data transfer over a ring. In our source-synchronous design, the clock and data NoC are routed in parallel yielding a fast, robust design. Architectural simulations on synthetic and real traffic show that our source-synchronous NoC designs can provide significantly lower latency while achieving the same or better bandwidth compared to a state of the art mesh, while consuming lower area. The fact that the our ring-based NoC runs significantly faster than the mesh contributes to these improvements. Moreover, since our proposed NoC designs are fully synchronous, they are very amenable to testing as well. In the last part of this dissertation, we explore an alternate scheme of achieving high-speed on-chip data transfer using sinusoidal signals of different frequencies. The key advantage of our method is the ability to superimpose such sinusoids and thereby effectively send multiple logic values along the same wire in a clock cycle. Experimental results show that for the same throughput as that of a traditional scheme, we require significantly fewer wires.

Dissertation (Ph.D.)--Auburn University, 2006. / Abstract. Includes bibliographic references (p.99-110).

Zugl.: Dortmund, Techn. Univ., Diss., 2009

Thesis (M.S.E.C.E.)--University of Massachusetts Amherst, 2008. / Includes bibliographical references (p. 68-73).

Erlangen, Nürnberg, Univ., Diss., 2007.

Stuttgart, Univ., Diss., 2002. / Erscheinungsjahr an der Haupttitelstelle: 2002. Computerdatei im Fernzugriff.