Gene transcription rates are influenced by proteins, known as Transcription Factors (TFs), that interact with DNA. The locations of TFs on the genome directly influence gene expression and the functional characteristics of a cell. TF binding locations can be estimated for entire genomes using high throughput chromatin immunoprecipitation sequencing (ChIP-Seq). While the analysis of ChIP-Seq binding locations is standardized for a single experiment, complications arise when data sets, taken from different labs and experimental conditions, are combined. In this thesis, I present my method for the simultaneous comparison of multiple ChIP-Seq data sets. My method of comparing multiple ChIP-Seq data sets extends the analysis of a single data set through the addition of two stages, a combination stage, and an extraction stage. Typically, one of two approaches are used to combine information from multiple datasets. Either estimated binding sites are extracted from each dataset and then combined (e.g. by various intersections or unions) or the "raw" genomic signals are analyzed by clustering or dimensionality reduction methods. Both approaches have strengths, but also substantial drawbacks. The method presented here relies both on estimating the binding sites and comparing the “raw” genomic signals between data sets. Once the binding locations have been found, the first step in the combination stage is to define an alternate feature space (AFS). The AFS is the union of all binding locations determined for all data sets. The AFS represents a subset of the genome that is likely to have TF binding in any condition where the protein is active. Once the AFS is defined, the read density is determined from the “raw” genomic signal of each of the data sets. The density is determined for all locations in the AFS resulting in a unified density matrix (UDM). The UDM is the final product of the combination stage of the analysis. After the data sets are homogenized into the UDM, the extraction stage is applied to the matrix. The extraction stage consists of applying machine learning techniques and other methods used to analyze the “raw” genomic signal, to help elucidate underlying similarities and differences between the data sets. I applied this method to the binding locations of the TF TAL1 across 22 ChIP-Seq data sets from the hematopoietic and endothelial lineages. Once the UDM had been generated and normalized, using quantile normalization, hierarchical clustering and principle component analysis (PCA) were applied. Clusters, formed by hematopoietic stem cells (HSCs), Erythroid, and T-cell acute lymphoblastic leukemia (T-ALL), were found using hierarchical clustering. The principle components (PCs) of the UDM provided weights for each peak. Using those weights I could separate groups of cellular conditions including T-ALL, Erythroid, HSC, and Endothelial Colony Forming Cells (ECFCs.) The weights also provided a quantitative measure of importance for each peak in the AFS based on how much weight they provided towards the group of interest. Functional analysis techniques, including de novo motif search and Gene Ontology, were applied to the peak partitions defined using the PCs. Motifs that were enriched in the T-ALL TAL1 partition, and not the Erythroid, were annotated and found to be similar to those that had previously been published, including Runx1 motif and a preference for the CC Ebox (CACCTG). In addition to finding the CC Ebox in T-ALL, I also show that it does not form a composite motif with GATA, indicating an alternative mechanism for the binding of TAL1 in T-ALL. This thesis establishes that heterogeneous collections of ChIP-Seq datasets, from multiple labs and experimental conditions, can be meaningfully combined, and provides an algorithmic template for doing so.

Due to the interplay between increasing chip capacity and complex applications, System-on-Chip (SoC) development is confronted by severe challenges, such as managing deep submicron effects, scaling communication architectures and bridging the productivity gap. Network-on-Chip (NoC) has been a rapidly developed concept in recent years to tackle the crisis with focus on network-based communication. NoC problems spread in the whole SoC spectrum ranging from specification, design, implementation to validation, from design methodology to tool support. In the thesis, we formulate and address problems in three key NoC areas, namely, on-chip network architectures, NoC network performance analysis, and NoC communication refinement. Quality and cost are major constraints for micro-electronic products, particularly, in high-volume application domains. We have developed a number of techniques to facilitate the design of systems with low area, high and predictable performance. From flit admission and ejection perspective, we investigate the area optimization for a classical wormhole architecture. The proposals are simple but effective. Not only offering unicast services, on-chip networks should also provide effective support for multicast. We suggest a connection-oriented multicasting protocol which can dynamically establish multicast groups with quality-of-service awareness. Based on the concept of a logical network, we develop theorems to guide the construction of contention-free virtual circuits, and employ a back-tracking algorithm to systematically search for feasible solutions. Network performance analysis plays a central role in the design of NoC communication architectures. Within a layered NoC simulation framework, we develop and integrate traffic generation methods in order to simulate network performance and evaluate network architectures. Using these methods, traffic patterns may be adjusted with locality parameters and be configured per pair of tasks. We propose also an algorithm-based analysis method to estimate whether a wormhole-switched network can satisfy the timing constraints of real-time messages. This method is built on traffic assumptions and based on a contention tree model that captures direct and indirect network contentions and concurrent link usage. In addition to NoC platform design, application design targeting such a platform is an open issue. Following the trends in SoC design, we use an abstract and formal specification as a starting point in our design flow. Based on the synchronous model of computation, we propose a top-down communication refinement approach. This approach decouples the tight global synchronization into process local synchronization, and utilizes synchronizers to achieve process synchronization consistency during refinement. Meanwhile, protocol refinement can be incorporated to satisfy design constraints such as reliability and throughput. The thesis summarizes the major research results on the three topics. / QC 20100525

La recherche dans le domaine de la génomique génère de données colossales dont la dimension ne cesse de s'accroître avec la technologie. Pour traiter cette masse d'information, la statistique est devenue un outil indispensable. Ce nouveau type de données représente un véritable challenge dans la mesure où ces données sont de très grande dimension, qu'elles sont très "bruitées" et qu'il n'existe généralement pas de "golden standard" permettant de valider les résultats. Au cours de cette thèse, nous nous sommes intéressés à l'analyse statistique de trois types de données : les puces à ADN, les ChIP-chip et les ChIP-Seq. Pour chacune d'entres elles, une nouvelle approche a été mise au point. Dans le cas des données de puces à ADN, la méthode GAGG permet de détecter les gènes différentiellement exprimés et de les grouper par type de profils. Pour ce faire, un Algorithme Génétique est utilisé de manière à optimiser deux critères liés à des méthodes voisines de l'ACP et des k-means. Pour les données de ChIP-chip, la méthode POTChIPS a été réalisée. Elle permet de repérer sur le génome, les sites de fixation d'une protéine d'intérêt (ex : un facteur de transcription). Dans cette méthode, une extraction des pics du signal est réalisée puis un seuil de significativité est déterminé à partir d'une modélisation POT. Enfin, pour ce qui est des données de ChIP-Seq, l'objectif est le même que pour les ChIP-chip, à savoir, repérer les sites de fixation d'une protéine sur l'ADN. La méthode POTSeq, mise au point au cours de cette thèse, est une adaptation de POTChIPS aux données de ChIP-Seq. / Research in Genomics produces very huge data which still increase with technology. Statistics is becoming essential to treat this amount of information. These new kind of data represent a great challenge in data analysis because of the great dimensions, the important background and the absence of "golden standard" which could allow to validate the obtained results. During this PhD thesis, we focused on statistical analysis for three kinds of data: DNA microarray, ChIP-chip and ChIP-Seq. For each one, a new approach have been proposed. For DNA microarrays, the GAGG method allows to detect differentially expressed genes and to cluster them by profile types. To do so, a Genetic Algorithm is used in order to optimize two criteria related to two nearby methods of PCA and $k$-means. In the case of ChIP-chip data, the POTChIPS method have been proposed. It allows to detect the binding sites of a protein of interest (a transcription factor e.g.) along the genome. In this method a peak extraction i realized then a significant threshold is obtained from a POT modelization. Finally, for ChIP-Seq data, the goal is the same that the one of chIP-chip, i.e., to find on DNA the binding sites of a protein of interest. The POTSeq method is an adaptation of POTChIPS for ChIP-Seq.La méthode POTSeq, mise au point au cours de cette thèse, est une adaptation de POTChIPS aux données de ChIP-Seq.

Myc is a powerful oncogene frequently deregulated in cancer yet deregulated Myc alone does not lead to cellular transformation due to the intrinsic safety mechanism of deregulated Myc potentiating apoptosis. The mechanism by which Myc potentiates apoptosis remains unclear, however, because the regions of Myc essential for apoptosis are also required for Myc to function as a regulator of gene transcription, it is thought that Myc’s role in apoptosis is a function of its regulation of an apoptotic genetic program. We hypothesize that under apoptotic conditions, Myc differentially binds and/or regulates a specific cohort of genes to potentiate apoptosis. The foremost approach to addressing this hypothesis is the employment of ChIP-chip coupled with expression microarray analyses. Here, using the MCF10A breast epithelial and SHEP neuroblastoma cell lines, we developed and characterized two independent human systems for subsequent ChIP-chip and expression array analyses to elucidate the genetic program of Myc-potentiated apoptosis.

Myc is a powerful oncogene frequently deregulated in cancer yet deregulated Myc alone does not lead to cellular transformation due to the intrinsic safety mechanism of deregulated Myc potentiating apoptosis. The mechanism by which Myc potentiates apoptosis remains unclear, however, because the regions of Myc essential for apoptosis are also required for Myc to function as a regulator of gene transcription, it is thought that Myc’s role in apoptosis is a function of its regulation of an apoptotic genetic program. We hypothesize that under apoptotic conditions, Myc differentially binds and/or regulates a specific cohort of genes to potentiate apoptosis. The foremost approach to addressing this hypothesis is the employment of ChIP-chip coupled with expression microarray analyses. Here, using the MCF10A breast epithelial and SHEP neuroblastoma cell lines, we developed and characterized two independent human systems for subsequent ChIP-chip and expression array analyses to elucidate the genetic program of Myc-potentiated apoptosis.

High performance systems have been widely adopted in many fields and the demand for better performance is constantly increasing. And the need of powerful yet flexible systems is also increasing to meet varying application requirements from diverse domains. Also, power efficiency in high performance computing has been one of the major issues to be resolved. The power density of core components becomes significantly higher, and the fraction of power supply in total management cost is dominant. Providing dependability is also a main concern in large-scale systems since more hardware resources can be abused by attackers. Therefore, designing high-performance, power-efficient and secure systems is crucial to provide adequate performance as well as reliability to users. Adhering to using traditional design methodologies for large-scale computing systems has a limit to meet the demand under restricted resource budgets. Interconnecting a large number of uniprocessor chips to build parallel processing systems is not an efficient solution in terms of performance and power. Chip multiprocessor (CMP) integrates multiple processing cores and caches on a chip and is thought of as a good alternative to previous design trends. In this dissertation, we deal with various design issues of high performance multiprocessor systems based on CMP to achieve both performance and power efficiency while maintaining security. First, we propose a fast and secure off-chip interconnects through minimizing network overheads and providing an efficient security mechanism. Second, we propose architectural support for fast and efficient memory protection in CMP systems, making the best use of the characteristics in CMP environments and multi-threaded workloads. Third, we propose a new router design for network-on-chip (NoC) based on a new memory technique. We introduce hybrid input buffers that use both SRAM and STT-MRAM for better performance as well as power efficiency. Simulation results show that the proposed schemes improve the performance of off-chip networks through reducing the message size by 54% on average. Also, the schemes diminish the overheads of bounds checking operations, thus enhancing the overall performance by 11% on average. Adopting hybrid buffers in NoC routers contributes to increasing the network throughput up to 21%.

Techn. Univ., Diss.--Dresden, 2002.

Additive manufacturing is revolutionizing the aerospace, transportation, energy, healthcare and various consumer product industries, replacing centralized manufacturing plants with more localized fabrication. 3D printing has become ubiquitous within these industries for prototyping and production. Currently, the smallest 3D printed features are on the order of a micron. While sufficient for some academic and industry applications, nanoscale features are required for the electronics industry and research endeavors. Optical lithography is still the workhorse for industrial nanofabrication utilizing large expensive commercial foundries. Here, an atomic scale 3D printer is presented with many of the features found in a complex semiconductor fabrication plant. This process is reproduced using three separate die with microelectromechanical systems (MEMS), which are bonded together to create an integrated 3D printer with the capability to print at the atomic scale. Due to the microscale size and surface areas of MEMS devices, they are extremely sensitive with rapid response times. These onboard MEMS devices replicate the functions of a thermal evaporator, patterning mask, mass sensor, heaters, temperature sensors and Van de Pauw setups. The assembled 3D printer dimensions are 3.8 mm x 2.5 mm x 1.8 mm (LxWxH) and it is therefore ideal for cryogenic environments. Quenched condensed thin film metals can be deposited using the atomic scale thermal evaporators in varying thicknesses up to approximately 50 nm. Replacing the atomic scale evaporators with microscale evaporators, the deposited film thickness can reach 3.5 microns. Evaporated films are monitored during and after the deposition with the embedded MEMS devices. While this particular 3D printing assembly is designed for research-scale investigations, the same technology could be extended to wafer-scale 3D printing with high resolution, rapid throughput, and reduced cost. / 2023-06-01T00:00:00Z

Yes / This paper proposes a new solution to improve the performance parameters of on-chip antenna designs on standard CMOS silicon (Si.) technology. The proposed method is based on applying the metasurface technique and exciting the radiating elements through coupled feed mechanism. The on-chip antenna is constructed from three layers comprising Si.-GND-Si. layers, so that the ground (GND) plane is sandwiched between two Si. layers. The silicon and ground-plane layers have thicknesses of 20μm and 5μm, respectively. The 3×3 array consisting of the asterisk-shaped radiating elements has implemented on the top silicon layer by applying the metasurface approach. Three slot lines in the ground-plane are modelled and located directly under the radiating elements. The radiating elements are excited through the slot-lines using an open-circuited microstrip-line constructed on the bottom silicon layer. The proposed method to excite the structure is based on the coupled feeding mechanism. In addition, by the proposed feeding method the on-chip antenna configuration suppresses the substrate losses and surface-waves. The antenna exhibits a large impedance bandwidth of 60GHz from 0.5THz to 0.56THz with an average radiation gain and efficiency of 4.58dBi and 25.37%, respectively. The proposed structure has compact dimensions of 200×200×45μm3. The results shows that, the proposed technique is therefore suitable for on-chip antennas for applications in system-on-chip for terahertz (THz) integrated circuits. / Innovation programme under grant agreement H2020-MSCA-ITN-2016 SECRET-722424; UK Engineering and Physical Sciences Research Council (EPSRC) under grant EP/E0/22936/1.

Efforts to increase productivity, reduce time to market, reduce costs and desire for increased functionality on a chip are driving semiconductor companies to consider SoC (System-on-a-chip) design. SoC offers the additional benefit of improving performance and design freedom. SoC designs are smaller, energy efficient and cheaper than the multi-chip solutions. Silicon manufacturing technology has improved to an extent where one can create a reliable chip with millions of transistors. Design of these complex systems, on the other hand, is taking longer and is much costlier even when the technology allows integration of the million transistor chips. Keeping these design costs low and reducing development cycle time is vital for any chip design company. Hence, companies need to delicately balance the design costs versus benefits for SoC design. Design turn-around time (TAT) even for large complex designs has been significantly improved by EDA tools despite the complexity added by the ever shrinking device geometries. However, other non technical issues and external dependencies in SoC design such as working with multi-disciplinary design teams, external IP (Intellectual Property) vendors, Electronic Design Automation (EDA) tool vendors and IP protection issues increase the risk of missing project goals and timeline. This paper will address both the technical and non-technical issues that arise when moving to SoC design and provide recommendations on how to address some of the non-technical issues involved. / text