This thesis presents the design and implementation of a CDR with 'phase reset.' By continually 'resetting' the phase of the recovered clock to be aligned with data, cycle-slipping and bit errors during the lock process are reduced. This concept was demonstrated in a full-rate 8-11Gb/s Bang-Bang CDR in 65nm CMOS.

This thesis presents the design and implementation of a CDR with 'phase reset.' By continually 'resetting' the phase of the recovered clock to be aligned with data, cycle-slipping and bit errors during the lock process are reduced. This concept was demonstrated in a full-rate 8-11Gb/s Bang-Bang CDR in 65nm CMOS.

This thesis introduces a new approach to compilation for FPGAs, which we call direct synthesis. We take a technology-mapped circuit netlist and directly map it into a pre-placed and routed FPGA overlay. Solving this problem may help to address the increasing portion of compile time that is attributed to placement and routing, and the tremendous amount of area and energy consumed by the highly flexible FPGA routing network. This thesis presents a direct synthesis algorithm and an algorithm for generating the pre-placed and routed FPGA overlays. Using the direct synthesis flow which we have designed, we can successfully map circuits less than 100 BLEs in size, after modest modi cations to the architecture of the FPGA overlay circuit. While we show that direct synthesis problem is challenging, further architectural modi cations are proposed which can allow the direct synthesis of larger circuits to succeed.

This dissertation explores a few techniques to realize a low-cost monolithic fiber-optic receiver with large-area photo detectors in advanced CMOS processes that could potentially support multi-gigabit digital data across 10 to 20 meters plastic optical fibers (POF). The first techniques investigated in this dissertation are the use of an external pseudo-differential photo detector chip to reduce the impact of the inductive parasitics, and the use of a cross-coupled regulated-cascode (CC-RGC) buffer to relieve the DC voltage headroom issues found in conventional regulated-cascode (RGC) buffers in technologies with low power supply voltages. The second technique investigated in this thesis is the super-Gm transimpedance amplifier (SGM-TIA) that can be used to produce a very small input impedance in order to drive a very large parasitic capacitance exhibited by an integrated photo detector in advanced CMOS processes. The third technique investigated is a linear equalizer with multiple shunt-shunt feedbacks that can be utilized to produce a slowly-rising peaking response in order to compensate for the frequency-dependent losses exhibited by the integrated NW/P-sub photo detector. Two prototype POF receiver test chips have been implemented in TSMC’s 65 nm CMOS processes and non-return-to-zero optical data transmissions have been demonstrated at data rates up to 3.125 Gbps and 4.25 Gbps, respectively, with a 2.5 Gbps grade 670 nm vertical-cavity surface-emitting laser based electro-optical transmitter.

This dissertation explores a few techniques to realize a low-cost monolithic fiber-optic receiver with large-area photo detectors in advanced CMOS processes that could potentially support multi-gigabit digital data across 10 to 20 meters plastic optical fibers (POF). The first techniques investigated in this dissertation are the use of an external pseudo-differential photo detector chip to reduce the impact of the inductive parasitics, and the use of a cross-coupled regulated-cascode (CC-RGC) buffer to relieve the DC voltage headroom issues found in conventional regulated-cascode (RGC) buffers in technologies with low power supply voltages. The second technique investigated in this thesis is the super-Gm transimpedance amplifier (SGM-TIA) that can be used to produce a very small input impedance in order to drive a very large parasitic capacitance exhibited by an integrated photo detector in advanced CMOS processes. The third technique investigated is a linear equalizer with multiple shunt-shunt feedbacks that can be utilized to produce a slowly-rising peaking response in order to compensate for the frequency-dependent losses exhibited by the integrated NW/P-sub photo detector. Two prototype POF receiver test chips have been implemented in TSMC’s 65 nm CMOS processes and non-return-to-zero optical data transmissions have been demonstrated at data rates up to 3.125 Gbps and 4.25 Gbps, respectively, with a 2.5 Gbps grade 670 nm vertical-cavity surface-emitting laser based electro-optical transmitter.

The verification of power grids in modern integrated circuits must start early in the design process when adjustments can be most easily incorporated. We adopt an existing early verification framework. The framework is vectorless, i.e., it does not require input test patterns and does not rely on simulating the power grid subject to these patterns. In this framework, circuit uncertainty is captured via a set of current constraints that capture what may be known or specified from circuit behavior. Grid verification becomes a question of finding the worst-case grid behavior which, in turn, entails the solution of linear programs (LPs) whose size and number is proportional to the size of the grids. The thesis builds on this systematic framework for dealing with circuit uncertainty with the aim of improving efficiency and expanding the capabilities handled within. One contribution introduces an efficient method based on a sparse approximate inverse technique to greatly reduce the size of the required linear programs while ensuring a user-specified over-estimation margin on the exact solution. The application of the method is exhibited under both R and RC grid models. Another contribution first extends grid verification under RC grid models to also check for the worst-case branch currents. This would require as many LPs as there are branches. Then, it shows how to adapt the approximate inverse technique to speed up the branch current verification process. A third contribution proposes a novel approach to reduce the number of LPs in the voltage drop and branch current verification problems. This is achieved by examining dominance relations among node voltage drops and among branch currents. This allows us to replace a group of LPs by one conservative and tight LP. A fourth contribution proposes an efficient verification technique under RLC models. The proposed approach provides tight conservative bounds on the maximum and minimum worst-case voltage drops at every node on the grid.

This thesis tackles the problem of high-speed data communication over wireline channels. Particular attention is paid to backplane channels which have impedance discontinuities and high-frequency loss. These channels require extra equalization effort in order to produce an open eye diagram at the receiver. Three signal processing techniques were investigated in the pursuit of higher data rates over backplane channels: transmit-side FIR filter equalization with variable tap spacing, bidirectional communication using frequency-division multiplexing, and an ADC-based receiver to provide a capability for non-linear equalization. The ADC presented here is a 5-bit flash ADC intended to be time-interleaved to attain a sufficient data rate. This ADC uses redundant comparators to obtain sufficient resolution without an explicit threshold tuning circuit. A resonant clocking line is used to reduce power and increase the maximum clock frequency.

This thesis presents a robust design approach for communication networks that includes capacitation and routing strategy design. Robustness is a mandatory property of core networks to respond to perturbations in network parameters for performance stability and reliable service delivery to different customers. Our proposed design approach is applicable to any system that is modelled by a weighted directed graph. To quantify the robustness measure, we borrow and develop different concepts and properties from Markov chain literatures as well as graph theory survivability discussions. We propose a new robustness definition for Markov chains. The new Markov chain robustness definition has different applications in network design. We define robustness as the sensitivity of the mean first passage time between any two states of the Markov chain. This sensitivity is measured based on the variations of the mean first passage times to the perturbations in transition probabilities. We show that this definition of robustness is related to the sensitivity of the betweenness of a node/state in a Markov chain, which is defined as the number of visits by a random walker that wanders around in the Markov chain according to its transition probabilities. It was shown that for an infinite walk, the proportion of number of visits to the total number of hops converges to the stationary probabilities. Therefore, an analogy can be seen between the well-known condition number and the robustness factor in a Markov chain. We also extend the robustness factor definition to network design problems. We show that the robustness factor can be used as a design criterion. The newly defined robustness factor is a function of the network capacitation, routing and external input and output traffic. We also emphasize the importance of the newly discovered graph theoretic metric, called the Kemeny constant, in network design problems. We discuss that a function of the Kemeny constant and robustness factor limits the sensitivity of network performance parameters to the perturbations in the network.

Simulations were carried out to determine the optical properties of 2 different layer structures which have been used in quantum well intermixed devices. The supported modes, effective refractive indices and optimal device dimensions prior to intermixing were reported. 1.5 micrometer ridge waveguides with 600 micrometer bend radii are shown to be suitable for minimizing loss. A first approximation to the intermixed structures were also simulated. An Asymmetric Mach-Zehnder Interferometer (AMZI) fabricated using a sputtered SiO2 Quantum Well Intermixing (QWI) process was also characterized. A 100 GHz channel spacing with an extinction ratio up to 16 dB was observed. Tuning of the device was achieved using current injection. A 0.45 nm tuning range was achieved at 15 mA of injected current. The design of a monolithically integrated all optical binary half-adder is also presented, with physical dimensions based on the results of the previous simulations.

Standard overcurrent protection schemes for passive radial systems assume single direction current flow. The addition of distributed generation (DG) presents issues for the protection scheme, as current can flow from multiple directions. This thesis investigates the impact of DGs on overcurrent protection designed for a radial system, and proposes solutions to address the issues. A realistic feeder system and its protection scheme are developed in PSCAD/EMTDC. A point-of-common-coupling (PCC) is identified, indicating the portion of feeder that can potentially operate as an island. One DG, with output adjusted to maintain a specified power flow at the PCC, is added to the feeder system. The performance of the overcurrent protection in the presence of line, ground, and three-phase faults is analyzed. A second machine, outputting full capacity at unity power factor, is added to the feeder system. The strategies used to develop the single-DG modified protection scheme are applied to the two-DG system. The functionality of the modified protection scheme is verified.