An SOI-based platform designed for wideband coupling of light from optical fibers to a 50 nm wide plasmonic slot waveguide is described in this thesis. The device is based on a newly proposed orthogonal junction with coupling efficiencies above 70% near the telecom wavelength. To construct the coupling platform, two such junctions are utilized for input and output, where Si wires are place 90 degree with respect to each of the two ends of a plasmonic section. Analytic studies and FDTD simulations have demonstrated attractive properties such as a smooth micron-wide transmission spectrum that can be spectrally shifted with the design parameters, and the natural phase-matching between the dielectric and plasmonic sections consequent of the waveguide orientations. Fabrication procedures and proof-of-concept characterization work are also presented. The experimentally-tested platform with its unique features would enable applications in on-chip sensing and plasmonic slot-based waveguiding at the 50 nm scale.

Ultra-wideband (UWB) wireless communication is a topic of intense research. It has the potential for superior performance over comparable narrowband wireless systems. UWB wireless systems transmit pulses that have energy concentrated mainly from 3.1 GHz to 10.6 GHz. These pulses are transmitted at very low energy levels so as not to interfere with many existing wireless systems that operate in the same band. UWB communication systems can benefit significantly from beamforming networks where the received signal strength depends on angle of arrival. This thesis focuses on the characterization of a digital beamformer in a real wireless channel. The beamformer is evaluated using various methods to judge its performance impact on a real UWB communication system. An analog UWB beamformer in hardware is derived by taking advantage of a simple microwave circuit realization. The analog UWB beamformer is studied and its feasibility is evaluated.

This thesis provides an investigation and review of homogeneous multilayer anti-reflective coatings (ARC) on glass. Recently, numerical optimization has become popular in optimizing the number of layers at a defined wavelength range and at angular incident angles. In this investigation, the design of the index profile is optimized for normal incident angle and angular incident angles by an evolutionary genetic algorithm. The anti-reflective coatings consist of multilayer porous silica or tin oxide nanoparticle films, which are fabricated by mixing 10nm silica nanoparticle or 10nm tin oxide nanoparticle colloidal solutions with varying amounts of 50nm polystyrene colloidal solutions, followed by spin coating on a glass substrate, and sintering at 400˚C for 40 minutes, which burns off the embedded polystyrene and renders a voided matrix. Experiments were carried out to produce ARCs based on well-known index profiles, and based on genetic algorithm optimization

The aim of this thesis is to establish a platform for implementing nanoscale plasmonic slot waveguide (PSW) devices that can interface with dielectric technology for hybrid silicon-plasmonic interconnect applications. For waveguide excitation, an orthogonal junction coupler that operates based on momentum matching is analyzed and then experimentally demonstrated to have coupling efficiency of 50 +/- 2 % between 450 nm wide silicon waveguide and 50 nm wide PSW across a 200 nm bandwidth. Next, for designing scalable optical components with multiple-input multiple-output capability and high fabrication tolerance, two dimensional PSW mesh structure that utilizes simultaneous power distribution and interference within a network of intersecting PSW junctions is introduced. Finally, a closed-form model for PSW mesh structures is derived by incorporating the characteristic impedance model into the scattering matrix formalism. The model can handle arbitrary combination of junctions and has less than 5 % discrepancy when compared to Finite-Difference Time-Domain results.

A variable (0.2 to 5 MHz) repetition rate femtosecond laser was applied to delineate the role of thermal diffusion and heat accumulation effects in forming low-loss optical waveguides in borosilicate glass across a broad range of laser exposure conditions. For the first time, a transition from thermal diffusion-dominated transport at 200-kHz repetition rate to strong heat accumulation at 0.5 to 2 MHz was observed to drive significant variations in waveguide morphology, with rapidly increasing waveguide diameter that accurately followed a simple thermal diffusion model over all exposure variables tested. Amongst these strong thermal trends, a common exposure window of 200-mW average power and ~15-mm/s scan speed was discovered across the range of 200-kHz to 2-MHz repetition rates for minimizing insertion loss despite a 10-fold drop in laser pulse energy. Waveguide morphology and thermal modeling indicate that strong thermal diffusion effects at 200 kHz give way to a weak heat accumulation effect at ~1uJ pulse energy for generating low loss waveguides, while stronger heat accumulation effects above 1-MHz repetition rate offered overall superior guiding. The waveguides were shown to be thermally stable up to 800°C, showing promise for high temperature applications. Using a low numerical aperture (0.4) lens, the effect of spherical aberration was reduced, enabling similar low-loss waveguides over an unprecedented 520-um depth range, opening the door for multi-level, three-dimensional, optical integrated circuits. In contrast to borosilicate glass, waveguides written in pure fused silica under similar conditions showed only little evidence of heat accumulation, yielding morphology similar to waveguides fabricated with low repetition rate (1 kHz) Ti-Sapphire lasers. Despite the absence of heat accumulation in fused silica owing to its large bandgap and high melting point, optimization of the laser wavelength, power, repetition rate, polarization, pulse duration and writing speed resulted in uniform, high-index contrast waveguide structures with low insertion loss. Optimum laser exposure recipes for waveguide formation in borosilicate and fused silica glass were applied to fabricate optical devices such as wavelength-sensitive and insensitive directional couplers for passive optical networks, buried and surface microfluidic and waveguide networks for lab-on-a-chip functionality, and narrowband grating waveguides for sensing.

This thesis proposes a low-IF receiver architecture suitable for the realization of single-chip receivers. To alleviate the image-rejection requirements of the front-end filters an oversampling complex discrete-time ΔΣ ADC with a signal-transfer function that achieves a significant filtering of interfering signals is proposed. A filtering ADC reduces the complexity of the receiver by minimizing the requirements of analog filters in the IF digitization path. Discrete-time ΔΣ ADCs have precise resonant frequency and clock frequency ratios and, hence, do not require the calibration or tuning that is necessary in the case of continuous-time ΔΣ modulator implementations. This feature makes the proposed discrete- time ΔΣ ADC ideal for multistandard receiver applications.

We present a novel automatic parallelization approach that uses traces. Our approach uses a binary representation of a program, allowing for the parallelization of programs even if their full source code is not available. Furthermore, traces can represent both iteration and recursion. We use hardware transactional memory (HTM) to ensure correct execution in the presence of dependences. We describe a parallel trace execution model that allows sequential programs to execute in parallel. In the model, traces are identified by a trace collection system (TCS), the program is transformed to allow the traces to execute on multiple processors, and the traces are executed in parallel. We present a framework with four components that, with a TCS, realizes our execution model. The grouping component groups traces into tasks to reduce overhead and make identification of successor traces easier. The packaging component allows tasks to execute on multiple processors. The dependence component deals with dependences on reduction and induction variables. In addition, transactions are committed in sequential program order on an HTM system to deal with dependences that are not removed. Finally, the scheduler assigns tasks to processors. We create a prototype that parallelizes programs and uses an HTM simulator to deal with dependences. To overcome the limitations of simulation, we also create another prototype that automatically parallelizes programs on a real system. Since HTM is not used, only dependences on induction and reduction variables are handled. We demonstrate the feasibility of our trace-based parallelization approach by performing an experimental evaluation on several recursive and loop-based Java programs. On the HTM system, the average speedup of the computational phase of the benchmarks on four processors is 2.79. On a real system, the average speedup on four processors is 1.83. Therefore, the evaluation indicates that trace-based parallelization can be used to effectively parallelize recursive and loop-based Java programs based on their binary representation.

The verification of power grids in modern integrated circuits must start early in the design process when adjustments can be most easily incorporated. We adopt an existing early verification framework. The framework is vectorless, i.e., it does not require input test patterns and does not rely on simulating the power grid subject to these patterns. In this framework, circuit uncertainty is captured via a set of current constraints that capture what may be known or specified from circuit behavior. Grid verification becomes a question of finding the worst-case grid behavior which, in turn, entails the solution of linear programs (LPs) whose size and number is proportional to the size of the grids. The thesis builds on this systematic framework for dealing with circuit uncertainty with the aim of improving efficiency and expanding the capabilities handled within. One contribution introduces an efficient method based on a sparse approximate inverse technique to greatly reduce the size of the required linear programs while ensuring a user-specified over-estimation margin on the exact solution. The application of the method is exhibited under both R and RC grid models. Another contribution first extends grid verification under RC grid models to also check for the worst-case branch currents. This would require as many LPs as there are branches. Then, it shows how to adapt the approximate inverse technique to speed up the branch current verification process. A third contribution proposes a novel approach to reduce the number of LPs in the voltage drop and branch current verification problems. This is achieved by examining dominance relations among node voltage drops and among branch currents. This allows us to replace a group of LPs by one conservative and tight LP. A fourth contribution proposes an efficient verification technique under RLC models. The proposed approach provides tight conservative bounds on the maximum and minimum worst-case voltage drops at every node on the grid.

This thesis tackles the problem of high-speed data communication over wireline channels. Particular attention is paid to backplane channels which have impedance discontinuities and high-frequency loss. These channels require extra equalization effort in order to produce an open eye diagram at the receiver. Three signal processing techniques were investigated in the pursuit of higher data rates over backplane channels: transmit-side FIR filter equalization with variable tap spacing, bidirectional communication using frequency-division multiplexing, and an ADC-based receiver to provide a capability for non-linear equalization. The ADC presented here is a 5-bit flash ADC intended to be time-interleaved to attain a sufficient data rate. This ADC uses redundant comparators to obtain sufficient resolution without an explicit threshold tuning circuit. A resonant clocking line is used to reduce power and increase the maximum clock frequency.

This thesis presents a robust design approach for communication networks that includes capacitation and routing strategy design. Robustness is a mandatory property of core networks to respond to perturbations in network parameters for performance stability and reliable service delivery to different customers. Our proposed design approach is applicable to any system that is modelled by a weighted directed graph. To quantify the robustness measure, we borrow and develop different concepts and properties from Markov chain literatures as well as graph theory survivability discussions. We propose a new robustness definition for Markov chains. The new Markov chain robustness definition has different applications in network design. We define robustness as the sensitivity of the mean first passage time between any two states of the Markov chain. This sensitivity is measured based on the variations of the mean first passage times to the perturbations in transition probabilities. We show that this definition of robustness is related to the sensitivity of the betweenness of a node/state in a Markov chain, which is defined as the number of visits by a random walker that wanders around in the Markov chain according to its transition probabilities. It was shown that for an infinite walk, the proportion of number of visits to the total number of hops converges to the stationary probabilities. Therefore, an analogy can be seen between the well-known condition number and the robustness factor in a Markov chain. We also extend the robustness factor definition to network design problems. We show that the robustness factor can be used as a design criterion. The newly defined robustness factor is a function of the network capacitation, routing and external input and output traffic. We also emphasize the importance of the newly discovered graph theoretic metric, called the Kemeny constant, in network design problems. We discuss that a function of the Kemeny constant and robustness factor limits the sensitivity of network performance parameters to the perturbations in the network.