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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

Design and implementation of an IEEE 1149.7-compliant cJTAG Controller for Debug and Trace Probe

Cabral, Carlos Javier 23 April 2013 (has links)
Debugging and testing today's complex processors and embedded systems provides many challenges. A Debug and Trace Probe with a standard interface to Target Systems (TS) can be used to debug and test both hardware and software components in complex systems. With a debug and trace probe information regarding the operation of the system can be obtained and analyzed to understand how the system is functioning and where problems may lie. This report presents an IEEE 1149.7-compliant cJTAG Controller design and implmentation for use in a Debug and Trace System (DTS). / text
2

Improved Signal Integrity in IEEE 1149.1 Boundary Scan Designs

Taboada, Efren De Jesus Rangel 04 November 2004 (has links) (PDF)
This work is an analysis of solutions to problems derived from inherent timing and signal integrity issues in the use and application of the IEEE 1149.1 Standard at the board level in conjunction with its test system. Setup or hold times violations may occur in a boundary scan chain using IEEE 1149.1 compliant devices. A practical study of the TDI-TDO scan data path has been conducted to show where problems may arise in relationship to a particular board topology and test system. This work points to differences between passing and failing scan path tests for problem characterization. Serial data flow is then analyzed and suitability is discussed. Within certain conditions, a solution is proposed. This work has been shown to work on the test system. Recommendations are made based on this experimental approach.
3

Univerzální programátor obvodů s rozhraním JTAG / Versatile Programmer of Components with JTAG Interface

Bartek, Lukáš January 2011 (has links)
This master's thesis deals with designing and implementation of universal programmer with JTAG interface. The project consists of a hardware and software part. Theoretical part discusses actual state in using the standards for programming and testing electronic devices, with special emphasis on JTAG implementation. Next part deals with programming ARM and FPGA devices through JTAG. The programming of this devices using available software is described in the practical part of this document. Final product of this work is the programmer itself. The programmer consists of the hardware and supplement software. At the end of this thesis there is a conclusion about possible improvements and development in the future.

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