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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

Design of a Highly Linear 24-GHz LNA

Elyasi, Hedieh 05 July 2016 (has links)
The increasing demand for high data rate devices and many applications in short range high speed communication, attract many RF IC designers to work on 24-GHz transceiver design. The Federal Communication Commission (FCC) also dedicates the unlicensed 24-GHz band for industrial, science, and medical applications to overcome the interference in overcrowded communications and have higher output signal power. LNA is the first building of the receiver and is a very critical building block for the overall receiver performance. The total NF and sensitivity of the receiver mainly depends on the LNAs NF that mandates a very low NF LNA design. Depending on its gain, the noise figure of the next stages can relax. However, the high gain of an LNA enforces the next stages to be more linear since they suffer from larger signal at their input stage and can get saturated easily. Apparently, designing high gain, low noise, and highly linear LNA is very stimulating. In this thesis, a wideband LNA with low noise figure and high linearity has been designed in 8XP 0.13-um SiGe BiCMOS IBM technology. The highlight of this design is proposing the peaking technique, which results in considerable linearity improvement. Loading the LNA with class AB amplifier, power gain experiences a peaking in high input signal swing levels. The next stager after the LNA is the buffer to provide isolation between the LNA and mixer, and also avoid loading of the LNA from the mixer. Instead of using popular emitter follower architecture, another circuit is proposed to have higher gain and linearity. This buffer has two separate out of phase inputs, coming from the LNA and are combined constructively at the output of the buffer. Since the frequency of this design is high, electromagnetic (EM) simulation for pads, interconnects, transmission lines, inductors, and coplanar transmission lines has been completed using Sonnet cad tool to consider all the parasitic and coupling effects. Considering all the EM effects, the LNA has 15 dB gain with 2.9 dB NF and -8.8 dBm input 1-dB compression point. The designed LNA is wideband, covering the frequency range of 12-GHz to 31-GHz. However, the designed LNA, has the capability of having higher gain at the expense of lower linearity and narrower frequency band using different control voltage. As an example peak gain of 29.3 dB at the 3-dB frequency range of 23.8 to 25.8-GHz can be achieved, having 2.3 dB noise figure and -17 dBm linearity. / Master of Science
2

Large signal model development and high efficiency power amplifier design in cmos technology for millimeter-wave applications

Mallavarpu, Navin 07 May 2012 (has links)
This dissertation presents a novel large signal modeling approach which can be used to accurately model CMOS transistors used in millimeter-wave CMOS power amplifiers. The large signal model presented in this work is classified as an empirical compact device model which incorporates temperature-dependency and device periphery scaling. These added features allow for efficient design of multi-stage CMOS power amplifiers by virtue of the process-scalability. Prior to the presentation of the details of the model development, background is given regarding the 90nm CMOS process, device test structures, de-embedding methods and device measurements, all of which are necessary preliminary steps for any device modeling methodology. Following discussion of model development, the design of multi-stage 60GHz Class AB CMOS power amplifiers using the developed model is shown, providing further model validation. The body of research concludes with an investigation into designing a CMOS power amplifier operating at frequencies close to the millimeter-wave range with a potentially higher-efficiency class of power amplifier operation. Specifically, a 24GHz 130nm CMOS Inverse Class F power amplifier is simulated using a modified version of the device model, fabricated and compared with simulations. This further demonstrates the robustness of this device modeling method.

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