In this thesis, a novel low-voltage, highly linear and tunable triode transconductor is introduced. The proposed transconductor with new structure is based on constant drain-source voltage method to operate at low-voltage. The proposed transconductor achieves wide linear input range up to 1.5V at 1.8V supply voltage and the total harmonic distortion is -61dB at 0.7Vpp. The design uses TSMC 0.18£gm CMOS technology and supply voltage as low as 1.6V. Moreover, it possesses large transconductance tuning range from 220£gS to 869£gS and also keeps the wide linear input range.

An ultra-low noise two-stage LNA design for cellular basestations using CMOS is proposed in this thesis work.  This thesis is divided into three parts. First, a literature survey which intends to bring an idea on the types of LNAs available and their respective outcomes in performances, thereby analyze how each design provides different results and is used for different applications. In the second part, technology comparison for 0.12µm, 0.18µm, and 0.25µm technologies transistors using the IBM foundry PDKs are made to analyze which device has the best noise performance. Finally, in the third phase bipolar and CMOS-based two-stage LNAs are designed using IBM 0.12µm technology node, decided from the technology comparison. In this thesis a two-stage architecture is used to obtain low noise figure, high linearity, high gain, and stability for the LNA. For the bipolar design, noise figure of 0.6dB, OIP3 of 40.3dBm and gain of 26.8dB were obtained. For the CMOS design, noise figure of 0.25dB, OIP3 of 46dBm and gain of 26dB were obtained. Thus, the purpose of this thesis is to analyze the LNA circuit in terms of design, performance, application and various other parameters. Both designs were able to fulfill the design goals of noise figure < 1 dB, OIP3 > 40 dBm, and gain >18 dB.

The increasing demand for high data rate devices and many applications in short range high speed communication, attract many RF IC designers to work on 24-GHz transceiver design. The Federal Communication Commission (FCC) also dedicates the unlicensed 24-GHz band for industrial, science, and medical applications to overcome the interference in overcrowded communications and have higher output signal power. LNA is the first building of the receiver and is a very critical building block for the overall receiver performance. The total NF and sensitivity of the receiver mainly depends on the LNAs NF that mandates a very low NF LNA design. Depending on its gain, the noise figure of the next stages can relax. However, the high gain of an LNA enforces the next stages to be more linear since they suffer from larger signal at their input stage and can get saturated easily. Apparently, designing high gain, low noise, and highly linear LNA is very stimulating. In this thesis, a wideband LNA with low noise figure and high linearity has been designed in 8XP 0.13-um SiGe BiCMOS IBM technology. The highlight of this design is proposing the peaking technique, which results in considerable linearity improvement. Loading the LNA with class AB amplifier, power gain experiences a peaking in high input signal swing levels. The next stager after the LNA is the buffer to provide isolation between the LNA and mixer, and also avoid loading of the LNA from the mixer. Instead of using popular emitter follower architecture, another circuit is proposed to have higher gain and linearity. This buffer has two separate out of phase inputs, coming from the LNA and are combined constructively at the output of the buffer. Since the frequency of this design is high, electromagnetic (EM) simulation for pads, interconnects, transmission lines, inductors, and coplanar transmission lines has been completed using Sonnet cad tool to consider all the parasitic and coupling effects. Considering all the EM effects, the LNA has 15 dB gain with 2.9 dB NF and -8.8 dBm input 1-dB compression point. The designed LNA is wideband, covering the frequency range of 12-GHz to 31-GHz. However, the designed LNA, has the capability of having higher gain at the expense of lower linearity and narrower frequency band using different control voltage. As an example peak gain of 29.3 dB at the 3-dB frequency range of 23.8 to 25.8-GHz can be achieved, having 2.3 dB noise figure and -17 dBm linearity. / Master of Science

This dissertation focuses on design and implementation of a highly linear and low flicker-noise receiver front-end based on the direct conversion architecture for multiband applications in a CMOS technology. The dissertation consists of two parts: One, implementation of a highly linear RF receiver front-end and, two, implementation of a low flicker-noise RF receiver front-end based for direct conversion architecture. For multiband applications, key active components, highly linear LNAs and mixers, in the RF front-end receiver have been implemented in a 0.18um CMOS process. Theoretical approaches are analyzed from the perspective of implementation issues for highly linear receiver system and are also compared with measured results. Highly linear LNAs and mixers have been analyzed in terms of noise, linearity and power consumption, etc. For a low flicker-noise receiver front-end based on direct conversion architecture, the design of differential LNA and various low flicker-noise mixers are investigated in a standard 0.18um CMOS process. A differential LNA which shows high linearity was fabricated with a low flicker-noise mixer. Three low flicker-noise mixers were designed, measured and compared to the-state-of-the-arts published by other research institutes and companies.