PIM - uma técnica onde elementos computacionais são adicionados perto, ou idealmente, dentro de dispositivos de memória - foi uma das tentativas criadas durante os anos 1990 visando mitigar o notório memory wall problem. Hoje em dia, com o amadurecimento do processo de integração 3D, um novo horizonte para novas arquiteturas PIM pode ser explorado. Para investigar este novo cenário, pesquisadores dependem de simuladores em software para navegar pelo espaço de exploração de projeto. Hoje, a maioria dos trabalhos que focam em PIM, implementam simuladores locais para realizar seus experimentos. Porém, esta metodologia pode reduzir a produtividade e reprodutibilidade. Neste trabalho, nós mostramos o desenvolvimento de um simulador de PIM preciso, modular e parametrizável. Nosso simulador, chamado CLAPPS, visa a arquitetura de memória HMC, uma memória 3D popular, que é amplamente utilizada em aceleradores PIM do estado da arte. Nós desenvolvemos nosso mecanismo utilizando a linguagem de programação SystemC, o que permite uma simulação paralela nativamente. A principal contribuição do nosso trabalho se baseia em desenvolver a interface amigável que permite a fácil exploração de arquiteturas PIM. Para avaliar o nosso sistema, nós implementamos um modulo de PIM que pode executar operações vetoriais com diferente tamanhos de operandos utilizando o proposto conjunto de ferramentas. / PIM - a technique which computational elements are added close, or ideally, inside memory devices - was one of the attempts created during the 1990s to try to mitigate the memory wall problem. Nowadays, with the maturation of 3D integration technologies, a new landscape for novel PIM architectures can be investigated. To exploit this new scenario, researchers rely on software simulators to navigate throughout the design evaluation space. Today, most of the works targeting PIM implement in-house simulators to perform their experiments. However, this methodology might hurt overall productivity, while it might also preclude replicability. In this work, we showed the development of a precise, modular and parametrized PIM simulation environment. Our simulator, named CLAPPS, targets the HMC architecture, a popular 3D-stacked memory widely employed in state-of-the-art PIM accelerators. We have designed our mechanism using the SystemC programming language, which allows native parallel simulation. The primary contribution of our work lies in developing a user-friendly interface to allow easy PIM architectures exploitation. To evaluate our system, we have implemented a PIM module that can perform vector operations with different operand sizes using the proposed set of tools.

Physical scaling limits of microelectronic devices and the need to improve electrical performance have driven significant research and development into 3D architecture. The development of die stacks in first level packaging is one of the more viable short-term options for improved performance. Placement of memory die above or below processors in a traditional flip chip C4 package with through-silicon vias (TSVs) has significant benefits in reducing data and power transmission paths. However, with the electrical performance benefits come great thermal and mechanical challenges. There are two key objectives for this work. The first is understanding of the die-die interface resistance, R[subscript dd], composed of the back end of line (BEOL) layers and micro-C4 interconnects. The interfacial resistance between BEOL material layers, the impact of TSVs and the impact of strain on R[subscript dd] are subtopics. The second key objective is the understanding of package thermal and mechanical behavior under operating conditions, such as local thermal disturbances. To date, these topics have not been adequately addressed in the literature. It is found that R[subscript dd] can be affected by TSVs, and that the interfacial contributions predicted by theoretical sub-continuum models can be significantly different than measurements. Using validated finite element models, the significance of the power distribution and R[subscript dd] on the temporal responses of 2D vs. 3D packages is highlighted. The results suggest local thermal hotspots can greatly exacerbate the thermal penalty due to the R[subscript dd] and that no peaks in stress arise in the transient period from power on to power off. / text

PIM - uma técnica onde elementos computacionais são adicionados perto, ou idealmente, dentro de dispositivos de memória - foi uma das tentativas criadas durante os anos 1990 visando mitigar o notório memory wall problem. Hoje em dia, com o amadurecimento do processo de integração 3D, um novo horizonte para novas arquiteturas PIM pode ser explorado. Para investigar este novo cenário, pesquisadores dependem de simuladores em software para navegar pelo espaço de exploração de projeto. Hoje, a maioria dos trabalhos que focam em PIM, implementam simuladores locais para realizar seus experimentos. Porém, esta metodologia pode reduzir a produtividade e reprodutibilidade. Neste trabalho, nós mostramos o desenvolvimento de um simulador de PIM preciso, modular e parametrizável. Nosso simulador, chamado CLAPPS, visa a arquitetura de memória HMC, uma memória 3D popular, que é amplamente utilizada em aceleradores PIM do estado da arte. Nós desenvolvemos nosso mecanismo utilizando a linguagem de programação SystemC, o que permite uma simulação paralela nativamente. A principal contribuição do nosso trabalho se baseia em desenvolver a interface amigável que permite a fácil exploração de arquiteturas PIM. Para avaliar o nosso sistema, nós implementamos um modulo de PIM que pode executar operações vetoriais com diferente tamanhos de operandos utilizando o proposto conjunto de ferramentas. / PIM - a technique which computational elements are added close, or ideally, inside memory devices - was one of the attempts created during the 1990s to try to mitigate the memory wall problem. Nowadays, with the maturation of 3D integration technologies, a new landscape for novel PIM architectures can be investigated. To exploit this new scenario, researchers rely on software simulators to navigate throughout the design evaluation space. Today, most of the works targeting PIM implement in-house simulators to perform their experiments. However, this methodology might hurt overall productivity, while it might also preclude replicability. In this work, we showed the development of a precise, modular and parametrized PIM simulation environment. Our simulator, named CLAPPS, targets the HMC architecture, a popular 3D-stacked memory widely employed in state-of-the-art PIM accelerators. We have designed our mechanism using the SystemC programming language, which allows native parallel simulation. The primary contribution of our work lies in developing a user-friendly interface to allow easy PIM architectures exploitation. To evaluate our system, we have implemented a PIM module that can perform vector operations with different operand sizes using the proposed set of tools.

PIM - uma técnica onde elementos computacionais são adicionados perto, ou idealmente, dentro de dispositivos de memória - foi uma das tentativas criadas durante os anos 1990 visando mitigar o notório memory wall problem. Hoje em dia, com o amadurecimento do processo de integração 3D, um novo horizonte para novas arquiteturas PIM pode ser explorado. Para investigar este novo cenário, pesquisadores dependem de simuladores em software para navegar pelo espaço de exploração de projeto. Hoje, a maioria dos trabalhos que focam em PIM, implementam simuladores locais para realizar seus experimentos. Porém, esta metodologia pode reduzir a produtividade e reprodutibilidade. Neste trabalho, nós mostramos o desenvolvimento de um simulador de PIM preciso, modular e parametrizável. Nosso simulador, chamado CLAPPS, visa a arquitetura de memória HMC, uma memória 3D popular, que é amplamente utilizada em aceleradores PIM do estado da arte. Nós desenvolvemos nosso mecanismo utilizando a linguagem de programação SystemC, o que permite uma simulação paralela nativamente. A principal contribuição do nosso trabalho se baseia em desenvolver a interface amigável que permite a fácil exploração de arquiteturas PIM. Para avaliar o nosso sistema, nós implementamos um modulo de PIM que pode executar operações vetoriais com diferente tamanhos de operandos utilizando o proposto conjunto de ferramentas. / PIM - a technique which computational elements are added close, or ideally, inside memory devices - was one of the attempts created during the 1990s to try to mitigate the memory wall problem. Nowadays, with the maturation of 3D integration technologies, a new landscape for novel PIM architectures can be investigated. To exploit this new scenario, researchers rely on software simulators to navigate throughout the design evaluation space. Today, most of the works targeting PIM implement in-house simulators to perform their experiments. However, this methodology might hurt overall productivity, while it might also preclude replicability. In this work, we showed the development of a precise, modular and parametrized PIM simulation environment. Our simulator, named CLAPPS, targets the HMC architecture, a popular 3D-stacked memory widely employed in state-of-the-art PIM accelerators. We have designed our mechanism using the SystemC programming language, which allows native parallel simulation. The primary contribution of our work lies in developing a user-friendly interface to allow easy PIM architectures exploitation. To evaluate our system, we have implemented a PIM module that can perform vector operations with different operand sizes using the proposed set of tools.

京都大学 / 新制・課程博士 / 博士(情報学) / 甲第23326号 / 情博第762号 / 新制||情||130(附属図書館) / 京都大学大学院情報学研究科通信情報システム専攻 / (主査)教授 大木 英司, 教授 守倉 正博, 教授 岡部 寿男 / 学位規則第4条第1項該当 / Doctor of Informatics / Kyoto University / DFAM

Depuis plusieurs années, la complexité des circuits intégrés ne cesse d'augmenter : du SOC (System On Chip) vers le SIP (System In Package), et plus récemment les circuits empilés en 3D : les 3D SIC (Stacked Integrated Circuits) à base de TSVs (Through Silicon Vias) interconnectant verticalement les tiers, ou puces, du système. Les 3D SIC présentent de nombreux avantages en termes de facteur de forme, de performance et de consommation mais demandent aussi de relever de nombreux défis en ce qui concerne leur test, étape nécessaire avant la mise en service de ces systèmes complexes. Dans cette thèse, nous nous attachons à définir les infrastructures de test qui permettront de détecter les éventuels défauts apparaissant lors de la fabrication des TSVs ou des différentes puces du système. Nous proposons une solution de BIST (Built In Self Test) pour le test avant empilement des TSVs. Cette solution est basée sur l'utilisation d'oscillateurs en anneaux dont la fréquence d'oscillation dépend des caractéristiques électriques des TSVs. La solution de test proposée permet non seulement la détection de TSVs fautifs mais aussi de renseigner sur le nombre d'éléments défectueux et leur identification. D'autre part, nous proposons une architecture de test 3D basée sur la nouvelle proposition de norme IEEE P1687. Cette infrastructure permet de donner accès aux composants du système 3D avant et après empilement. Elle permet d'autre part de profiter du recyclage des données de test développées et appliquées avant empilement pour chacun des tiers puis ré-appliqués durant ou après l'empilement. Ces travaux aboutissent finalement à l'ouverture d'une nouvelle problématique liée à l'ordonnancement des tests sous contraintes (puissance consommée, température).Mots-clés : test, circuits 3D, TSV, BIST, oscillateur en anneau, architecture de test 3D, IEEE P1687, test avant empilement, test après empilement. / For several years, the complexity of integrated circuits continues to increase, from SOC (System On Chip) to SIP (System In Package) , and more recently 3D SICs (Stacked Integrated Circuits) based on TSVs (Through Silicon Vias ) that vertically interconnect stacked circuits in a 3D system. 3D SICs have many advantages in terms of small form factor, high performances and low power consumption but have many challenges regarding their test which is a necessary step before the commissioning of these complex systems. In this thesis we focus on defining the test infrastructure that will detect any occurring defects during the manufacturing process of TSVs or the different sacked chips in the system. We propose a BIST (Built In Self Test) solution for TSVs testing before stacking, this solution is based on the use of ring oscillators which their oscillation frequencies depend on the electrical characteristics of the TSVs. The proposed test solution not only allows the detection of faulty TSVs but also gives information about the number of defective TSVs and their location. On the other hand, we propose a 3D DFT (Design For Test) architecture based on the new proposed test standard IEEE P1687. The proposed test architecture provides test access to the components of the 3D system before and after stacking. Also it allows the re-use of recycled test data developed and applied before stacking to each die in the mid-bond and post-bond test levels. This work lead to the opening of a new problem related to the test scheduling under constraints such as: power consumption, temperature.Keywords: test, 3D circuits, TSV, BIST, ring oscillators, 3D DFT architecture, IEEE P1687, pre-bond test, post-bond test.

Many cutting-edge computer and electronic products are powered by advanced Systems-on-Chip (SoC). Advanced SoCs encompass superb performance together with large number of functions. This is achieved by efficient integration of huge number of transistors. Such very large scale integration is enabled by a core-based design paradigm as well as deep-submicron and 3D-stacked-IC technologies. These technologies are susceptible to reliability and testing complications caused by thermal issues. Three crucial thermal issues related to temperature variations, temperature gradients, and temperature cycling are addressed in this thesis. Existing test scheduling techniques rely on temperature simulations to generate schedules that meet thermal constraints such as overheating prevention. The difference between the simulated temperatures and the actual temperatures is called temperature error. This error, for past technologies, is negligible. However, advanced SoCs experience large errors due to large process variations. Such large errors have costly consequences, such as overheating, and must be taken care of. This thesis presents an adaptive approach to generate test schedules that handle such temperature errors. Advanced SoCs manufactured as 3D stacked ICs experience large temperature gradients. Temperature gradients accelerate certain early-life defect mechanisms. These mechanisms can be artificially accelerated using gradient-based, burn-in like, operations so that the defects are detected before shipping. Moreover, temperature gradients exacerbate some delay-related defects. In order to detect such defects, testing must be performed when appropriate temperature-gradients are enforced. A schedule-based technique that enforces the temperature-gradients for burn-in like operations is proposed in this thesis. This technique is further developed to support testing for delay-related defects while appropriate gradients are enforced. The last thermal issue addressed by this thesis is related to temperature cycling. Temperature cycling test procedures are usually applied to safety-critical applications to detect cycling-related early-life failures. Such failures affect advanced SoCs, particularly through-silicon-via structures in 3D-stacked-ICs. An efficient schedule-based cycling-test technique that combines cycling acceleration with testing is proposed in this thesis. The proposed technique fits into existing 3D testing procedures and does not require temperature chambers. Therefore, the overall cycling acceleration and testing cost can be drastically reduced. All the proposed techniques have been implemented and evaluated with extensive experiments based on ITC’02 benchmarks as well as a number of 3D stacked ICs. Experiments show that the proposed techniques work effectively and reduce the costs, in particular the costs related to addressing thermal issues and early-life failures. We have also developed a fast temperature simulation technique based on a closed-form solution for the temperature equations. Experiments demonstrate that the proposed simulation technique reduces the schedule generation time by more than half.

Ces dernières décennies, l'industrie en microélectronique s'est astreinte à suivre la loi de Moore pour améliorer la performance des circuits intégrés (Integrated Circuit, IC). Cependant, il sera sans doute impossible de suivre cette loi dans le futur à cause de limitations physiques apparaissant avec la miniaturisation des transistors en-dessous d'un certain seuil si aucune innovatio n'a lieu. Afin de surmonter ce problème, de nouvelles technologies ont émergées, et parmi elles les circuits 3D (3D-Stacked Integrated Circuit, 3D-SIC) ont été proposés pour maintenir l'évolution de la loi de Moore. Les 3D-SIC peuvent apporter de nombreux avantages dans le design des futurs IC mais au coût d'une complexité de design accrue étant donné leur nature fortement combinatoire, et l'optimisation de plusieurs critères conflictuels. Dans cette thèse, nous présentons une première étude des outils qui pourraient aider dans le design de 3D-SIC, en utilisant l'optimisation multi-objectifs (multiobjective optimization, MOO) et l'aide multicritère à la décision (multi-criteria decision aid, MCDA). Notre étude vise l'une des problématiques principales dans le design de 3D-SIC: le partitionnement avec estimation du floorplanning en tenant compte de plusieurs objectifs. Cette thèse montre que l'utilisation d'un paradigme multicritère peut fournir une analyse pertinente et objective du problème. Cela peut permettre une exploration rapide de l'espace de design et une amélioration des flots de conception actuels étant donné qu'il est possible de fournir des informations qualitatives et quantitatives par rapport à l'espace de design qui ne seraient pas disponibles avec les outils actuels. De même, de par sa flexibilité, la MOO peut tenir compte des multiples degrés de liberté des 3D-SIC, ce qui permet plus de possibilités de design qui ne sont généralement pas prises en compte avec les outils actuels. De plus, les algorithmes développés peuvent montrer des propriétés de robustesse même si le problème est complexe. Enfin, appliquer l'aide multicritère à la décision pourrait permettre aux designers de faire des choix pertinents selon un processus transparent. / In the past decades, the microelectronic industry has been following the Moore's law to improve the performance of integrated circuits (IC). However, it will probably be impossible to follow this law in the future due to physical limitations appearing with the miniaturization of the transistors below a certain threshold without innovation. In order to overcome this problem, new technologies have emerged, and among them the 3D-Stacked Integrated Circuits (3D-SIC) have been proposed to keep the Moore's momentum alive. 3D-SICs can bring numerous advantages in the design of future ICs but at the cost of additional design complexity due to their highly combinatorial nature, and the optimization of several conflicting criteria. In this thesis, we present a first study of tools that can help the design of 3D-SICs, using mutiobjective optimization (MOO) and multi-criteria decision aid (MCDA). Our study has targeted one of the main issues in the design of 3D-SICs: the partitioning with floorplanning estimation under multiple objectives. This thesis shows that the use of a multi-criteria paradigm can provide relevant and objective analysis of the problem. This can allow a quick design space exploration and an improvement of the current design flows as it is possible to provide qualitative and quantitative information about a design space, that would not be available with current tools. Also, with its flexibility, MOO can cope with the multiple degrees of freedom of 3D-SICs, which enables more design possibilities that are usually not taken into account with current tools. In addition, the developed algorithms can show robustness properties even if the problem is complex. Finally, applying multi-criteria decision aid would allow designers to make relevant choices in a transparent process. / Doctorat en Sciences de l'ingénieur / info:eu-repo/semantics/nonPublished