Semiconductors are vital components in the challenge of harvesting solar power to provide sufficient carbon neutral energy for a growing global population. A trend in semiconductor devices is to nanostructure some of the layers in order to obtain improvements in optical and electrical properties. This work focusses on two materials that have been gaining academic and commercial interest over a number of years. Zinc oxide (ZnO) is a wide bandgap semiconductor that can be grown via a number of physical and chemical deposition methods; the work on ZnO builds upon research on a chemical growth route which can create well aligned hexagonal rods with diameters from ~20 nm to Illm, with lengths of hundreds of nanometres to tens of microns. Changes in the growth solution led to either aligned or disordered rods, but the irreproducibility of the technique is evident. The second material studied is indium gallium nitride (InxGa1-xN), a semiconductor which can have its optoelectronic properties tuned by changing the ratio of In to Ga. Tuneable bandgaps are desirable for absorbing the optimum fraction of solar energy. Photoelectrochemistry is used to probe the optoelectronic characteristics of the semiconductors and theoretical models are used to simulate the combination of the optics and electronics in nanostructured electrodes, with waveguiding effects being shown to alter the expected efficiency of photoelectrochemical reactions in nanorods. A model based on the semiconductor continuity equation and Shockley-Read-Hall recombination is developed to describe the time dependent photoelectrochemical current of semiconductors with mid-band defect states, as functions of applied potential and illumination intensity. From the model a novel technique is provided to calculate the position and density of the defect states; the technique is successfully demonstrated on ZnO nanorods for the first time and evaluated for its effectiveness .

This work investigates the impact of electronic trapping on AIGaN/GaN high electron mobility transistor (HEMT) degradation, particularly through the analysis of electric field strength in devices. The demand for ever increasing power capabilities in semiconductor microwave and power switching applications requires an understanding of the physics underlying degradation mechanisms within GaN-based HEMTs in order to be able to develop structures capable to exploit GaN's power capabilities. The investigation of high electric field induced mechanisms therefore contributes to research efforts to increase the power capabilities of state of the art AIGaN/GaN HEMTs. Electrical stressing was performed on AIGaN/GaN HEMTs fabricated on the same epitaxial material to alleviate growth-to-growth variations in the experimental results. Analysis of electrical characterisation before and after electrical stress as well as IV-assisted recovery of different gate geometries showed a tendency towards electronic trap generation depending on the location of the peak electric field. Drift-diffusion simulations confirmed that the peak electric field location was in turn dependent on the gate shape. Device degradation was seen to be most detrimental for peak fields located by the SiNx / AIGaN interface. For better estimation of the electric field strength responsible for degradation through surface trapping, a method using liquid crystal was developed to detect the electric field strength at the surface of the device. This method enabled the verification of drift-diffusion simulations, generally used for electric field strength estimation in AIGaN/GaN HEMTs, by exploiting the ability of molecules in a nematic liquid crystal suspension to respond to an external electric field by aligning according to the field lines. Visualising the set-up through crossed polarisers resulted in images of the drain access region at increasing source-drain bias with dark areas showing molecule alignment. Critical conditions at which maximum molecule alignment in the film was seen, corresponded with simulated results. Due to the direct relationship between the two gimensional ~lectron ~as (2DEG) channel and surface states in AIGaN/GaN devices and the report of a suggested surface passivation straininduced effect on gate leakage currents, AIGaN/GaN HEMTs with complete and partially etched surface passivation layers were investigated with photoluminescence, Raman spectroscopy while pulsed I-V characteristics. Significant additional or reduced strains due to surface passivation, could not be detected in the upper layers of the device excluding a strain-related mechanism, and pulsed I-V characteristics found little surface trapping, but evidence of AIGaN barrier and buffer trapping in these particular devices. Finally, the question of how to create a high power device based on GaN without the need for expensive large scale lateral device designs was addressed by electrically characterising the GaN/GaAs interface, suggesting the use of a GaAs drain substrate for a vertical power GaN device. Following theoretical predictions of a GaN/GaAs conduction band alignment proposing Ohmic interface conduction, experimental results suggest instead the presence of an energy barrier at the interface, the origin of which is not clear. Suggested mechanisms include Nitrogen diffusion resulting in a bandgap variation at the GaN/GaAs interface and the influence of polarisation effects due to a highly strained GaN layer.

In this thesis we use optical spectroscopy to investigate III/V semiconductor quantum dot-micropillar cavities. The aim is to identify a pillar containing a single quantum dot that can be used to develop an optical switch, an important component within a photonic network. We will investigate how to improve the mode-coupling of a laser beam into the micropillar cavity, to increase the efficiency of coupling photons into and out of the cavity. We will develop and demonstrate the micropillar post-processing techniques performed using a Focussed Ion Beam etching technique to control the mode-splitting within a micropillar that arises from an imperfect cavity with an elliptical cross-section. Finally, we will investigate how a quantum dot strongly coupled to the micropillar cavity mode can be used as an optical switch.

Recent years have seen a surge in interest into the properties of new materials, and their application in electronic devices. This project has used techniques common for colloidal systems in order to gain insight into these systems. The work has mainly focussed on single-walled carbon nanotubes (SWCNTs), however silicon nanowires have also briefly been studied. Pluronic block copolymers are commonly used to stabilise SWCNTs in water, most commonly F127. Such dispersions were studied using small-angle neutron scattering (SANS) experiments performed at a range of solvent contrast systems. The data were successfully fitted to a relatively simple core-shell cylinder model. Data fitting was consistent with SWCNTs present in small bundles in dispersion, with an average radius of 10 A, surrounded by a water-swollen F127 layer of 61 A thickness, with a water content of 94% in the adsorbed layer. Increasing the temperature of F127 /SWCNT /D20 systems so that they were above the critical micellisation temperature (CMT) of the polymer was seen to have only a small impact on the polymer adsorption, with the adsorbed layer thickness increasing from ~55 to 65 A, and the adsorbed amount increasing by between 50 and 100% (from ~ 1 to 1.5 mg m- 2). Dispersions of SWCNTs in surfactant mixtures of SDS and sodium cholate (SC) are often used to separate SWCNTs by electronic type. SWCNTs were dispersed with SDS and studied using small-angle scattering techniques at various contrasts. Data were fitted to a core-shell cylinder model, and the fits were consistent with small SWCNT bundles of an average radius of 10 A, surrounded by an adsorbed layer of thickness 18 A. The adsorbed amount of SDS at the SWCNT surface was calculated to be 2.5 mg m-2 , however the adsorbed amount at the SDS headgroup/water interface was calculated to be 0.85 mg m- 2 , a value closer to previously reported values for the adsorption of SDS on carbon surfaces. Subsequently, SWCNTs dispersed with SC and mixtures of SDS and SC (1:4 and 3:2 volume ratios of SDS:SC) were studied with SANS, and the dimensions of the decorated SWCNTs were not seen to vary greatly between the different surfactants studied. Finally, the separation of nanoparticles has been investigated. The separation of SWCNTs based on their electronic properties using aqueous PEG/dextran twophase polymer systems was studied. Although absorbance spectra suggested that an electronic separation of SWCNTs had occurred, the process was found to be highly irreproducible. Additionally, variations in temperature were found to have little effect on partitioning and no separation by electronic type was seen when F127-dispersed SWCNTs rather than SC-stabilised SWCNTs were used, suggesting that, unlike F127, SC adsorbs differently to SWCNTs depending on their electronic type. Silicon nanowires (SiNWs) have also been briefly studied, and separating the nanowires by length was attempted using glass bead columns, however no significant separation by length was achieved.

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Photovoltaic panels (PV) are being used increasingly to reduce the carbon impact of new single-storey industrial buildings. This thesis investigates the application of PV panels in conjunction with an asymmetric building shape to optimise the design of a single-storey building for net-zero carbon. The design optimisation of both symmetrical and asymmetrical steel portal frames is considered. Three different types of portal frame were considered, those made from: rolled sections (Le. Universal Beams), fabricated sections welded from three plates, and finally, fully tapered sections. The benefit of increased solar radiation on the southward side in addition to the asymmetry allows for improved carbon offsetting potential, which is a very desirable attribute for buildings attempting to meet the new tighter net-zero carbon compliance levels. Asymmetry has been shown to allow building configurations with lower embodied energy with similar carbon offsetting performance to symmetric or less asymmetric counterparts. Asymmetry was shown to allow for both material and therefore cost savings without changing the building footprint. The structural steel weight was found to have a minimal impact on the energy optimisation. However, the energy optimisation has significant impact on the structural design as it determines the optimum degree of asymmetry. This means that a recommendation of uncoupled design optimisations is made where first an energy optimisation is used with an estimated steel weight to identify a favourable asymmetry configuration (up to 80%) for the steel design to use within its own optimisation. This method would be of particular use in the code compliance of new zero carbon non domestic single storey steel buildings

This thesis presents results of a study of ZnS:Mn thin film phosphors used in Thin Film ELectroluminescent (TFEL) and Laterally Emitting TFEL (LETFEL) devices, examining techniques for phosphor growth optimisation and post deposition processing in order to strengthen development of novel TFEL devices. To achieve this, thin films of phosphor were deposited using RF magnetron sputtering to investigate the use of co-sputtering in order to optimise dopant concentration. 800 nm films of ZnS:Mn were simultaneously co-sputtered from ZnS and ZnS:Mn (1 wt.%) solid targets. The thin films were deposited at different manganese concentrations by varying the relative RF power applied to each target. The films were deposited directly onto 100 mm diameter (100) n-type silicon substrates, or onto a layer of 300 nm of Y2O3 to fabricate electroluminescent test devices. Luminescence from the phosphor films was characterised via photoluminescent excitation using a 337 nm pulsed N2 laser, with the photoluminescence (PL) optimum obtained at 0.38 ZnS:Mn power ratio. Electroluminescence (EL) from TFEL devices were excited by applying a sinusoidal waveform voltage at a frequency of 1 kHz with maximum luminance obtained at 0.36 ZnS:Mn power ratio.

The electrical noise phenomenon in semiconductor devices has been an on-going research topic throughout the evolution of semiconductors, having been discovered in the characteristics of a vacuum tube [1]. Being a naturally occurring phenomenon, due to the microscopic interaction of conducting carriers with defects in the lattice structure, electrical noise can never be eliminated completely. Instead the degree of current/voltage fluctuations can only be reduced if the noise origin is known and well-understood. Amongst the types of electrical noise identified, the low frequency or 1/f noise is the most studied phenomenon, owing to the valuable insight that it gives in relation to the degree of crystal perfection, structural quality of fabricated devices and device reliability; as well as its impact and disturbance on circuit operation. In this thesis, the focus is on exploring the characteristics of low frequency noise on electronic devices made using silicon carbide, in particular, a high temperature signal-level junction field effect transistor (JFET), and 2D graphene film utilising an epitaxially grown graphene field effect transistor (GFET). One of the advantages of using SiC electronics is its ability to operate at higher temperatures than conventional Si and SOI technologies, where theoretical predictions of operation above 800°C and practical device operation up to 600°C have been demonstrated [2]–[5]. The realisation of high temperature devices opens up a new opportunity for functional electronic systems in hostile environment applications, such as in space exploration, geothermal/geo-exploration plus monitoring capability and thermal/nuclear reactor inspection. As one of the key design considerations in analogue circuits, the low frequency noise defines the minimal recoverable input signal of an amplifier, limits the down-scaling of signal level & transistor sizes, and affects the RF circuit operation in the form of phase noise. In the effort to facilitate the transistor optimisation process in enabling functional SiC electronics in extreme environment, the electrical noise origins of JFET with 9μm and 21μm gate length with multiple gate width dimensions were investigated. The noise behaviours of the transistor variants are each dominated by the generation-recombination (G-R) process and contribution of resistive noise components. Furthermore, the temperature dependence of the JFETs noise characteristics measured from 300K to 700K can be distinctively correlated to each JFET variants, where the trap assisted G-R mechanism and the low-field mobility-temperature dependence can be used to describe the acquired results correspondingly. Abstract v In the effort to deploy SiC electronics in extreme environment, it is imperative to first understand the electrical performance and lifetime of SiC devices, when subjected to prolonged operating conditions. This is useful to pinpoint the expected operational lifetime and ensure the reliability of these critical electronic components. Whilst, the DC and AC characteristics may offer a restricted amount of information on the level of device degradation, any abnormality in device operation can be better detected by low frequency noise measurements, where the degree of noise deviation between the good and damaged devices often exceeds those observed using DC and AC parameters. The reliability of SiC JFETs subjected to 1000 hours of high temperature stressing was examined utilising both current-voltage and low frequency noise behaviour. The degraded device structures of the stressed SiC JFETs can be successfully segregated by comparing the low frequency noise and current-voltage characteristics between the aged and as-fabricated samples. It was found that the degradation of contact metallisation governed the transistor noise properties at drain-source voltages ≤1.25V and the enhanced multi level G-R process from traps generated in the active transistor structures dominate the noise at drain-source voltages >1.25V. Graphene has gained a significant amount of research attention in recent years, owing to its superlative material properties. The ultra high carrier mobility, large surface to volume ratio, and potentially ultra low noise property, position graphene as an attractive candidate in fabricating remarkable switching devices and sensor nodes that surpass current state-of-the-art technology. Whilst, the ideal graphene characteristics may seem extraordinary, in practice the actual device properties do not match theoretical predictions, due to the material synthesis and device fabrication processes, which introduce unintentional defects into the system. The influence of gate dielectric formation is investigated by correlating noise measurements with conventional DC and AC parametric testing. The obtained noise results illustrate that the normalised current noise magnitude shows a power dependency with the channel resistance. An enhanced hysteresis effect is also observed for epitaxial GFETs that can be correlated to the quality of the graphene/oxide interface formed during gate dielectric formation. The Hall Effect mobility and noise properties of these GFETs were mapped on wafer scale (16mm×16mm) to examine the material and device reproducibility and repeatability for large scale manufacturing. The inverse relation between the GFETs low frequency noise and the Hall Effect mobility and the weak sheet resistance dependence on the sheet electron concentration, implies a short-range mobility scattering related noise origin.