Pure Mn and Mn/MgF₂ cermet films (50 to 1500A thick) containing between 10 and 100 Wt% Mn have been prepared by single boat evaporation in vacuo ≤ 10⁻⁵ torr. All films studied are ohmic, and the resistivity lying between 100 µΩ-cm and 10 mΩ-cm. Within this range, the resistivity decreases non-linearly with increase in film thickness and increase in Mn content. The effect on the film resistivity of other deposition parameters, viz substrate temperature, residual gas pressure, annealing and aging are investigated. The structure of the films was investigated using X-ray diffraction and transmission electron microscopy. Films with negative TCR have low activation energies (~ 1 to 100 meV) in the temperature range 110 to 720K, and the electronic conduction mechanism in these films is probably electron tunnelling and/or percolation depending on film composition, thickness and annealing temperature.

A nanowire is a thin wire with a cross section conveniently measured in nanometres (nm). It has a large surface area to volume ration which allows it to have more exposure to the environment. Therefore, it is highly desirable to be implemented as a biosensor as it would exhibit a characteristic of being ultra-sensitive and highly selective to a wide range of biological and chemical species.

The turn on behaviour of thyristors resulting from the application of a gate pulse is described. From this investigation a thyristor model is developed which enables the computation of the anode - cathode voltage and anode current during turn on. Comparisons are made between the measured and computed waveforms for many different circuits including series and parallel operation of thyristors.

No description available.

The serial interface is a pervasive component within many electronic products and will be familiar to users of personal computers and modern electronic devices. Over the last twenty years, the serial interface or link has developed from a specialist electronic subsystem for computer and telecommunication systems to an essential building block for modern electronic products ranging from disk storage devices to home entertainment consoles. The high speed serial interface (HSS!) offers fast data transfer at relatively low cost and is now an semiconductor vendors supplying chips to original equipment manufacturers.

The advent of carbon nanotube (CNT) synthesis has created exciting new oppor- tunities in fluid dynamic applications as the fluid behaviour can deviate signifi- cantly from conventional continuum expectations. CNTs indicate major potential in nanotechnologies such as seawater desalination. Molecular dynamics (MD) is often the numerical method of choice for fluid dynamics at the nanoscale due to its high level of detail and accuracy. Using the “controllers” of Borg et al.[1], we are able to shrink the computa- tional domain required for molecular dynamic simulations of the external flow of liquid argon past a CNT and significantly increase the simulation’s computational efficiency. We apply three pressure differences across a CNT membrane carrying liquid argon, and compare the results of the pressure-driven flow through the nanotube with hydrodynamic predictions and Navier-Stokes solutions. We find that both fail to accurately predict flow behaviour in this problem. Non-equilibrium molecular dynamics simulations are then used to investigate water transport through (7,7) CNTs, investigating how changing the CNT length affects the internal flow dynamics. We show that, under the same applied pressure difference, an increase in CNT length has a negligible effect on the resulting mass flow rate and fluid flow velocity. Axial profiles of fluid properties demonstrate that entrance and exit effects are significant in the transport of water along CNTs. Large viscous losses in these entrance/exit regions lead into central “developed” regions in longer CNTs where the flow is effectively frictionless. Finally, we investigate how changing the number of structural defects in the wall of a (7,7) single-wall carbon nanotube (CNT) affects the water transport and internal fluid dynamics. Structural defects are modelled as vacancy sites (missing carbon atoms). We find that, while fluid flow rates exceed continuum expectations, increasing numbers of defects lead to significant reductions in fluid velocity and mass flow rate. The inclusion of such defects disrupts the nearly- frictionless water transport commonly attributed to CNTs. The results presented in this thesis are crucial in the development of future nanotechnologies such as CNT membranes for selective material separation.

Zinc oxide (ZnO) and Indium Gallium Zinc Oxide (IGZO) thin films are of interest as oxide semiconductors in thin film transistor (TFT) applications, due to visible light transparency, and low deposition temperature. There is particular interest in ZnO and IGZO based transparent TFT devices fabricated at low temperature on low cost flexible substrates. However, thermal annealing processes are typically required to ensure a good performance, suitable long term stability, and to control the point defects which affect the electrical characteristics. Hence there is interest in post deposition processing techniques, particularly where alternatives to high temperature thermal treatments can be utilised in combination with low temperature substrates. This thesis presents the results of a series of experimental studies as an investigation into photonic (excimer laser) processing of low temperature ZnO and IGZO thin films deposited by RF magnetron sputtering and/or by high target utilisation sputtering (HiTUS), to optimise the microstructure and electrical properties for potential use in thin film electronic applications. ZnO thin films were grown at various deposition parameters by varying oxygen flow rates, RF power, oxygen concentration, and growth temperatures. Subsequently, the films were subjected to three different annealing processes: (i) Thermal Annealing (furnace): samples were thermally annealed in air at temperatures ranging from 300 °C to 880 °C for 1 hour. (ii) Rapid Thermal Annealing: samples were annealed in nitrogen and oxygen environment at temperatures of 600 °C, 740 °C, 880 °C, and 1000 °C, and dwell times of 1-16 s. (iii) Excimer laser annealing: samples were annealed at ambient conditions using a Lambda Physik 305i 284 nm, 20 ns pulse KrF excimer laser with a beam delivery system providing a homogenised 10 mm x 10 mm uniform irradiation at the sample plane. Processing was undertaken at fluences in the range of 0 to 350 mJ/cm2 at single and multiple pulses. IGZO thin films were also investigated following RF magnetron deposition without intentional substrate heating and at various other deposition conditions, followed by laser processing in air at laser energy densities in the range of 0 to 175 mJ/cm2 with single pulse. Processed ZnO films were characterised by room temperature photoluminescence excitation which exhibited that laser annealing at high fluences resulted in suppression of the observed visible deep level emission (DLE) with evolution of a strong UV near band emission (NBE) peak, indicating a reduction of intrinsic defects without film degradation or materials loss that occurred by thermal and rapid thermal annealing. Also the intensity of the NBE peak was strongly influenced by the films growth temperature, with the results showing that as the growth temperature increased beyond ambient; the intensity of the resultant NBE peak decreased as a function of laser energy. TEM studies demonstrate that laser processing provides a controlled in-depth crystallisation and modification of ZnO films. Therefore, laser processing is shown to be a suitable technique to control the crystal microstructure and defect properties as a function of two lasers processing parameters (fluence, number of pulses) - realising optimised film properties as a localised region isolated from the substrate or sensitive underlying layers. In terms of electrical properties, the results indicated a significant drop in sheet resistance as a function of laser anneal from highly resistive (>5 MΩ/sq.) to about 860 Ω/sq. To produce IGZO thin films without intentional substrate heating with lowest sheet resistance as a function of laser processing, low deposition pressure, low oxygen concentration, and high RF power are required. Room temperature Hall effect mobility of 50 nm thick IGZO increased significantly as the laser energy density increased from 75 mJ/cm2 to 100 mJ/cm2 at single pulse reaching values of 11.1 cm2/Vs and 13.9 cm2/Vs respectively.

This Thesis presents research undertaken to investigate the electro-optical characterisation and optimisation of Thin Film Electroluminescent (TFEL) devices and Laterally Emitting Thin Film Electroluminescent (LETFEL) devices with respect to device lifetime and aging. Post deposition localised laser annealing as an alternative to thermal annealing has been previously described in the literature. The effects of laser annealing on various devices is investigated and described within this Thesis. In particular, the novel use of ArF laser annealing at a wavelength of 193nm as a post deposition annealing process for ZnS:Mn thin films deposited by RF magnetron sputtering has been presented and compared to KrF laser annealing (248nm wavelength). Additionally the use of KrF laser annealing on a new deposition method, High Target Utilisation Sputtering (HiTUS) is presented, with successful results obtained on heat sensitive substrates. Results presented show that the use of KrF produces slightly better performance in respect to maximum luminance, however the use of ArF laser annealing can allow for achievement of higher luminance at lower applied voltages. Research is also presented regarding methods for tackling the issue of reduced performance of devices over time. Investigations are undertaken to determine the extent to which the burn-in parameters used affect the lifetime of devices. A series of experiments in which the step-time, voltage and therefore overall burn-in time are altered are described. Results show that the lifetime of the device can be significantly altered by small changes to these parameters, with significant improvements in lifetime observed and described. As a result of the experiments and analysis described in this Thesis, areas for further research are suggested with the aim of further device optimisation in regards to post deposition heat treatment and the burn-in process.

Parametric variability increasingly affects the performance of electronic circuits as the fabrication technology has reached the level of 32nm and beyond. These parameters may include transistor Process parameters (such as threshold voltage), supply Voltage and Temperature (PVT), all of which could have a significant impact on the speed and power consumption of the circuit, particularly if the variations exceed the design margins. As systems are designed with more asynchronous protocols, there is a need for highly robust synchronizers and arbiters. These components are often used as interfaces between communication links of different timing domains as well as sampling devices for asynchronous inputs coming from external components. These applications have created a need for new robust designs of synchronizers and arbiters that can tolerate process, voltage and temperature variations. The aim of this study was to investigate how synchronizers and arbiters should be designed to tolerate parametric variations. All investigations focused mainly on circuit-level and transistor level designs and were modeled and simulated in the UMC90nm CMOS technology process. Analog simulations were used to measure timing parameters and power consumption along with a “Monte Carlo” statistical analysis to account for process variations. Two main components of synchronizers and arbiters were primarily investigated: flip-flop and mutual-exclusion element (MUTEX). Both components can violate the input timing conditions, setup and hold window times, which could cause metastability inside their bistable elements and possibly end in failures. The mean-time between failures is an important reliability feature of any synchronizer delay through the synchronizer. The MUTEX study focused on the classical circuit, in addition to a number of tolerance, based on increasing internal gain by adding current sources, reducing the capacitive loading, boosting the transconductance of the latch, compensating the existing Miller capacitance, and adding asymmetry to maneuver the metastable point. The results showed that some circuits had little or almost no improvements, while five techniques showed significant improvements by reducing τ and maintaining high tolerance. Three design approaches are proposed to provide variation-tolerant synchronizers. wagging synchronizer proposed to First, the is significantly increase reliability over that of the conventional two flip-flop synchronizer. The robustness of the wagging technique can be enhanced by using robust τ latches or adding one more cycle of synchronization. The second approach is the Metastability Auto-Detection and Correction (MADAC) latch which relies on swiftly detecting a metastable event and correcting it by enforcing the previously stored logic value. This technique significantly reduces the resolution time down from uncertain synchronization technique is proposed to transfer signals between Multiple- Voltage Multiple-Clock Domains (MVD/MCD) that do not require conventional level-shifters between the domains or multiple power supplies within each domain. This interface circuit uses a synchronous set and feedback reset protocol which provides level-shifting and synchronization of all signals between the domains, from a wide range of voltage-supplies and clock frequencies. Overall, synchronizer circuits can tolerate variations to a greater extent by employing the wagging technique or using a MADAC latch, while MUTEX tolerance can suffice with small circuit modifications. Communication between MVD/MCD can be achieved by an asynchronous handshake without a need for adding level-shifters.

This thesis presents my work on the fabrication of nanocrystalline silicon (nc-Si) thin film transistors and characterization of their stability under different conditions. Nc-Si transistors are promising alternative to the current amorphous silicon (a-Si:H) devices, especially in areas where a-Si:H TFTs are reaching the performance ceiling, e.g. new large area applications such as active matrix organic light emitting diode displays (AMOLED). This is mostly due to the superior nc-Si properties – high carrier mobility and good electrical stability stemming from the crystalline Si grains embedded in a disordered a-Si:H matrix. Another large advantage of nc-Si TFTs over competing materials is the full compatibility with the a-Si:H fabrication base. Nanocrystalline silicon is a relatively new material and some aspects require further investigation before industrial applications. The pool of knowledge on nc-Si devices is especially shallow for the electrical stability of bottom gate TFTs under prolonged illumination which is important for several thin film applications, such as AMOLED and phototransistors. This issue was selected as the main topic of the thesis. Top gate TFTs were also designed, fabricated, characterized and compared to the bottom gate transistors. The electrically detected magnetic resonance method was employed to investigate the nc-Si/dielectric structures and it was shown that it can be used to evaluate the TG TFT channel/dielectric interface.