The aim of this thesis is to understand and optimise the optoelectronic properties of InP quantum dot laser diodes which operate in the range around 730nm required for various application such as the photodynamic therapy. The properties of wafers with two barrier widths, 8 and 6nm, each grown at different temperatures, 690, 710, 730 and 750T, and consisting of 5 layers of dots forms from different quantity of deposited material, 2, 2.5 and 3ML, are described and investigated. The laser and multisection devices of these structures are used to determine threshold current density, lasing wavelength, modal absorption, modal gain and spontaneous emission spectra. The modal absorption spectra show three different dot size distributions, small, large and very large dots. Their variation with growth temperature results in a blue shift accompanied by an increasing number of states while the variation with quantity of deposited material shows only an increase to the number of states. The lasing wavelength variation with growth temperature covers a range between 715–745nm. The threshold current density as a function of temperature for 2000/m long laser devices grown at temperature of 750°C exhibits a distinctive dependence on the operating temperature and becomes less pronounced when the growth temperature reduces. This is explained in terms of the carrier distributions in the quantum dot and quantum well states without invoking an effect from Auger recombination. The optimisation of threshold current density can be reached by using structures with higher barrier width grown at low temperature and deposited with high quantity of quantum dot material to minimise both the affect of the very large dot, which contain a number of defects associated with them, and carrier leakage from quantum dot to quantum well states. This reduces the room temperature threshold current density to ISO A/cm 2 for 2mm long lasers with uncoated facets.

Magnetic materials, especially thin films, are being exploited today in many engineering applications such as magnetic recording heads and media, magnetic sensors and actuators and even magnetic refrigeration due to their smaller form factor or to thin film effects that do not occur in bulk material. Hence there is a need for optimised growth of thin films to suit the requirements of applications. The aim of this research work is two-fold: 1. Growth and characterisation of optimised magnetic thin films using pulsed-laser deposition and 2. Extension of Jiles-Atherton (JA) theory of hysteresis. A series of magnetoelastic thin films based on cobalt ferrite were deposited on SiO2/Si(100) substrates using pulsed-laser deposition at different substrate temperatures and different reactive oxygen pressures. The crystal structure, composition, magnetic properties, microstructure and magnetic domains of cobalt ferrite thin films were investigated. The optimised growth conditions of poly crystalline spinel cobalt ferrite thin films were determined from characterisation results. The Curie point of the optimised cobalt ferrite thin film was determined from moment vs. temperature measurement. The optimised thin film was magnetically annealed in order to induce an in-plane uniaxial anisotropy. The magnetostriction of the optimised sample was determined in the vibrating sample magnetometer using the inverse measurement technique. A special 3-point bender was designed and built for this purpose. The first successful thin film of Gd5Si2Ge2, a magnetocaloric rare earth intermetallic alloy, was deposited on a polycrystalline AlN substrate. The crystal structure, composition and magnetic phase transformation of Gd5Si2Ge2 thin film were investigated. The preliminary results are furnished in this thesis. The JA model of hysteresis was extended to incorporate thermal dependence of magnetic hysteresis. The extended model was validated against measurements made on substituted cobalt ferrite material. A functional form of anhysteretic magnetisation was derived. The JA theory was also extended to model magnetic two-phase materials. This proposed model was qualitatively compared with measured data published in the literature. The JA theory was applied to magnetoelastic thin films. The cobalt ferrite thin films deposited on SiO2/Si(100) substrates at different substrate temperatures and oxygen pressures have been modelled based on JA theory and were validated against measurements. This model would help in understanding the influence of deposition parameters on properties of thin films. The calculated and measured data were in excellent agreement.

With an aim to investigate methods to realise low thermal-budget fabrication of aluminium doped zinc oxide (AZO) and indium gallium zinc oxide (IGZO) thin films, a dual step fabrication process was studied in this research. Initially, an experimental programme was undertaken to deposit AZO and IGZO films by radio frequency (RF) magnetron sputtering with no external substrate heating and at a wide range of deposition parameters including oxygen to argon ratio, RF power, and sputtering pressure. Thereafter, the samples were subjected to post-depositing annealing in air at ambient temperature utilising the advantages of excimer laser annealing (ELA) with a pulsed krypton fluoride (KrF) excimer laser at different laser fluences and number of pulses. The electrical, structural, compositional, and optical properties of the fabricated samples were systematically investigated as a function of the fabrication (deposition and annealing) conditions. A range of thin film characterisation techniques was used including 4-point probe (4PP), Van der Pauw (VDP), Hall Effect, X-ray diffraction (XRD), X-ray photoelectron spectroscopy (XPS), Atomic-force microscopy (AFM), Energy-dispersive X-ray spectroscopy (EDX), and optical transmittance and reflectance spectroscopy. Sputter-deposition of AZO and IGZO at room temperature revealed that the electrical properties of the deposited films are profoundly controlled by the deposition conditions applied. Low sputtering pressure of 2 mTorr is desired to obtain the best quality materials. However, high RF power of 180 W (4 W/cm2) is required to produce AZO with enhanced crystallinity, high electron density, and thus low resistivity. While, moderate RF power of 50 W (1.1 W/cm2) is applied to produce amorphous IGZO films with moderate-to-high resistivity suitable for thin film transistors (TFTs). The oxygen to argon ratio is found to have the most significant impact on defining the electrical properties for both AZO and IGZO. The resistivity of IGZO films was dependant on their metallic composition which in turn is controlled by the deposition conditions. TFTs were fabricated on silicon substrates with 40 nm thick IGZO as the active layer deposited at room temperature and different growth conditions. TFT performance was largely affected by the active layer deposition conditions. TFTs with the optimised IGZO, deposited at 50 W and 2 mTorr of 2% oxygen to argon ratio, exhibited a field effect mobility of 0.67 cm2/Vs, an on/off current ratio of 5x105, a turn on voltage of -0.15 V, and a subthreshold swing S of 0.28 V/decade. Upon ELA, AZO showed a resistivity reduction which is shown to result from increasing both the free electron density and mobility. When the optimised as-deposited AZO, 180 nm thick deposited at 180 W and 2 mTorr of 0.2% oxygen to argon ratio, annealed with 5 pulses at 125 mJ/cm2, a 50% resistivity reduction to 5x10-4 Ω.cm was obtained. It was demonstrated that average grain size increase, oxygen related defects decrease, and aluminium activation in doped ZnO are the origin of the AZO resistivity reduction upon ELA. Rapid thermal annealing (RTA) was also examined on AZO; RTA in nitrogen at 300°C for 20s increased the AZO gain size and doping efficiency leading to similar resistivity reduction to that achieved by the optimised ELA. Both ELA and RTA enhanced the AZO visible transmission to > 85 %, while the near infrared transmission was degraded due to higher electron density after annealing. The electro-optical properties of the optimised AZO samples obtained by ELA and RTA, which are very close to those of standard tin doped indium oxide (ITO), demonstrate the viability of AZO as an attractive transparent conducting material for various electronic applications. The potential use of AZO for photovoltaics (PVs) as well as the AZO stability against damp heat exposure were also examined. PVs with optimised ELA and RTA treated AZO samples showed comparable power conversion efficiency (PCE) to that of PVs with high-quality commercial ITO. The damp heat stability of AZO samples was strongly dependant on the fabrication conditions. In regard to IGZO, ELA increased the free electron density and mobility leading to better conductivity, while the amorphous structure is maintained. ELA with single pulse at a low energy density of 30 mJ/cm2 resulted in an improved performance for IGZO TFTs on silicon substrates achieving a field effect mobility of 3.33 cm2/Vs, an on/off current ratio of 3x107, a turn on voltage of +0.35 V, and a subthreshold swing S of 0.27 V/decade. Moreover, ELA was successfully applied to IGZO TFTs on polymer flexible PEN leading to TFTs with enhanced performance. Hence, a combination of RF magnetron sputtering at room temperature and ELA, which are both efficiently applicable to thin films mass production, has been demonstrated to provide a low thermal budget fabrication route for functional materials including AZO, as the most promising substitute to ITO in a wide range of applications, and IGZO as the most attractive material for TFT applications. This combination is an alternative thin film fabrication route to using elevated substrate temperature or post-deposition thermal annealing typically applied in the dominant literature reports, to obtain thin films with suitable characteristics.

Minimisation of Intermodulation Distortion (IMD), and in particular the third order IMD, in communication systems is key to developing linearisation methods. The first step in the minimisation process is the characterisation of the extrinsic and intrinsic device nonlinearities that give rise to the IMD phenomena. Many conventional analytical characterisation methods are too complex to interpret whilst schematic characterisation provides very little information as to how the results are derived. The above issues are addressed in this thesis through the development of an analytical IMD model for the microwave InGAP/GaAs DHBT. The model is based on Taylor series expansion of intrinsic device nonlinearities, mainly the base› emitter dynamic resistance (Rbe), base-emitter diffusion capacitance (Cciff), voltage controlled current source (VCCS) and the base-collector depletion capacitance (Cbe). Data derived from this model is compared with measurements, calculations and simulations of both weak and relatively strong nonlinearities. It is shown that a simple diode model is robust enough to account for the IMD behaviour at low powers and frequencies. However, at higher powers and frequencies the Taylor series based model needs to be adopted. Through this model it is found that the VCCS non linearity is reasonably sufficient in explaining IMD phenomena at low powers. However, at higher input signal power levels and frequencies the Cbe nonlinearity is found to dominate to such an extent that it almost completely accounts for the characteristics of the dip in the third order IMD. Another area where very little research is conducted is the thermal analysis of nonlinear behaviour. Hence, third order IMD (which is the most problematic from a filtering viewpoint) measurements are made as a function of temperature. These results are compared with the data derived using the Taylor series based model as well as the purely resistive diode model. The relationship between device parameters, biasing and IMD behaviour is critical when designing for linearity. Hence, during this project a novel method is developed for the extraction of thermal resistance, directly at the point of optimum bias (where third order IMD is minimised). This technique is compared with the traditional methods of extracting thermal resistance and it is found to have the added advantage of being able to extract thermal resistance at lower power dissipations and temperatures.

With the emergence of multichannel/multimedia communication service, RF and microwave products are being driven by ever increasing demands for higher powers, higher efficiency, lower costs, smaller size, and shorter time-to-market. RF and microwave monolithic ICs with Heterojunction Bipolar Transistors (HBTs) and High Electron Mobility Transistors (HEMTs) as backbones is one of the best solutions that can meet this demand. As the range of applicability of these devices increases it becomes imperative to have efficient and accurate device models which include various effects. In this thesis the small signal characteristics of InGaP/GaAs DHBTs and AIGaAs/lnGaAs/GaAs pHEMTs have been analysed and modelled for the first time using a newly developed automated procedure. The . parameter extractions for HBTs and HEMTs over varying bias and temperature conditions were implemented using Agilent’s Integrated Circuit Evaluation, Characterisation and Analysis Program (IC-CAP). The novelty of this work lies in the simple flow developed which is applicable to any given device over a wide bias, frequency and temperature range. A maturity in the conventional small signal model is presented based on the analysis and this is validated for the RF performance of the fabricated DHBTs and pHEMTs. Emphasis has been made on the temperature analysis and novel results of device parameters are discussed that govern the speed and power handling capabilities of these components. The temperature dependant data is highly valuable when developing temperature susceptible circuits such as power amplifiers, cryogenically cooled low noise amplifiers etc. This data also provides an insight into the material properties that is very important in selecting the right material for a specific application. The physical origin of degradation in performance of the transistor characteristics with temperature is discussed in detail and modelled empirically. For the first time the effect of frequency on the small signal characteristics of these devices is discussed in detail which conventionally is considered to be frequency independent. The developed linear temperature dependent small signal model of the AIGaAs/lnGaAs/GaAs pHEMT is used to design a broadband amplifier operating at 8GHz bandwidth covering bluetooth and wireless applications.

This thesis proposes techniques to mitigate multiple bit errors in GF arithmetic circuits. As GF arithmetic circuits such as multipliers constitute the complex and important functional unit of a crypto-processor, making them fault tolerant will improve the reliability of circuits that are employed in safety applications and the errors may cause catastrophe if not mitigated. Firstly, a thorough literature review has been carried out. The merits of efcient schemes are carefully analyzed to study the space for improvement in error correction, area and power consumption. Proposed error correction schemes include bit parallel ones using optimized BCH codes that are useful in applications where power and area are not prime concerns. The scheme is also extended to dynamically correcting scheme to reduce decoder delay. Other method that suits low power and area applications such as RFIDs and smart cards using cross parity codes is also proposed. The experimental evaluation shows that the proposed techniques can mitigate single and multiple bit errors with wider error coverage compared to existing methods with lesser area and power consumption. The proposed scheme is used to mask the errors appearing at the output of the circuit irrespective of their cause. This thesis also investigates the error mitigation schemes in emerging technologies (QCA, CNTFET)to compare area, power and delay with existing CMOS equivalent. Though the proposed novel multiple error correcting techniques can not ensure 100% error mitigation, inclusion of these techniques to actual design can improve the reliability of the circuits or increase the dif culty in hacking crypto-devices. Proposed schemes can also be extended to non GF digital circuits.

The driving factor behind this research was to design & develop a line driver capable of meeting the demanding specifications of the next generation of SerDes devices. In this thesis various line driver topologies were analysed to identify a topology suited for a high-speed low-voltage operating environment. This thesis starts of by introducing a relatively new high-speed communication Device called SerDes. SerDes is used in wired chip-to-chip communications and operates by converting a parallel data stream in a serial data stream that can be then transmitted at a higher bit rate, existing SerDes devices operate up to 12.5Gbps. A matching SerDes device at the destination will then convert the serial data stream back into a parallel data stream to be read by the destination ASIC. SerDes typically uses a line driver with a differential output. Using a differential line driver increases the resilience to outside sources of noise and reduces the amount of EM radiation produced by transmission. The focus of this research is to design and develop a line driver that can operate at 40Gbps and can function with a power supply of less than IV. This demanding specification was decided to be an accurate representation of future requirements that a line driver in a SerDes device will have to conform to. A suitable line driver with a differential output was identified to meet the demanding specifications and was modified so that it can perfonn an equalisation technique called pre-distortion. Two variations of the new topology were outlined and a behavioural model was created for both using Matlab Simulink. The behavioural model for both variants proved the concept, however only one variant maintained its perfomance once the designs were implemented at transistor level in Cadence, using a 65nm CMOS technology provided by Texas Instruments. The final line driver design was then converted into a layout design, again using Cadence, and RC parasitics were extracted to perfom a post-layout simulation. The post layout simulation shows that the novel line driver can operate at 40Gbps with a power supply of 1 V - O.8V and has a power consumption of 4.54m W /Gbps. The Deterministic Jitter added by the line driver is 12.9ps.

Emerging wide bandgap (WBG) power transistors are capable of improving the efficiency of mains voltage power electronic circuits. Several commercial WBG transistors are now available, but all exhibit undesirable gate drive characteristics. The cascode circuit has been suggested as a solution to this problem: WBG cascodes improve the switching speed, gate characteristics and noise immunity of devices, at the expense of greater on-state resistance. WBG cascodes have not, however, been widely accepted in commercial applications. Previous research has typically been too application-specific, with little practical information available for design engineers wishing to use them. This thesis addresses these shortcomings through a comprehensive investigation of practical design considerations for switch-mode cascode circuits. A SPICE simulation and simplified mathematical model are developed as design tools to give a detailed insight into cascode hard-switching behaviour and to aid cascode optimisation and device selection. The effects of the cascode configuration on static (DC) device performance are quantified for a silicon super-junction (SJ) metal-oxide-semiconductor field-effect transistor (MOSFET), silicon carbide (SiC) junction field-effect transistor JFET and SiC MOSFET. The on-state resistance penalty of the cascode configuration is shown to be modest and potentially mitigated by careful selection of HV transistor gate bias. There are few advantages to using silicon SJ MOSFETs in a cascode configuration, but both SiC MOSFET and JFET cascodes benefit from improved gate drive, reverse conduction and switching characteristics. SiC MOSFETs are shown to be better suited to efficient high temperature operation, while SiC JFETs are more appropriate for high current applications. Cascode switching losses are shown to be reduced compared to standalone devices, although reverse recovery losses can counteract this. Methods of controlling switching transients using gate resistors or feedback capacitors are investigated and shown to be effective. The effects of stray inductance on cascode switching are quantified experimentally for the first time. This corroborates other work and informs the layout of cascode circuits. The resilience of cascodes to severe dV/dt is also demonstrated. The findings of this thesis are summarised in a practical design guide aimed at design engineers who wish to use this useful circuit.

Scaling of electronic devices is driven, from the consumption side, by the need for compact electrical products, increase in device speed and from the production side, by lowering of production cost. However, aggressive scaling gives rise, among others, to high gate tunnelling currents in contemporary silicon dioxide (SiO2) based Metal-Oxide- Field Effect Transistors (MOSFETs). SiO2 is therefore expected to be replaced in future technologies with alternative dielectrics. Several dielectrics with high dielectric constants (high-κ) are being studied as candidates for integration into transistors. It is desirable that any dielectric that replaces SiO2 contains as much as possible the electrical properties for which the SiO2 dielectric has been so important in FET technology: high band-offset, low oxide/interface state density and consequently high mobility. However, mobility in transistors with high-κ gate dielectrics is generally lowered compared to their SiO2–based counterparts. Several factors are known to cause mobility degradation in SiO2-based MOSFETs. These include effect of charge scattering centres on the dielectric/Si interface as well as substrate ionized impurities. Also contributing to mobility reduction is phonon scattering, that is, vibration of lattice bonds. In this thesis, samples of high-κ based MOSFETs and MOS capacitors (MOS-C) were experimentally studied for causes of mobility reduction. The study was focused on devices of hafnium silicate gate dielectrics. The nature of interface traps in Hf silicate was completely characterized by determining the interface state density as well as the trap capture cross section. The interface state density levels in the devices was experimentally determined by use of two high resolution techniques: the ac conductance and the charge pumping techniques. Both methods gave similar values of mean interface state density, indicating the accuracy of the experimentally determined mean interface density in the Hf silicate dielectric. Additionally, the ac conductance method established the detailed interface trap distribution profile in Si energy band gap for the Hf silicate dielectric. This study represents the first in depth study of the nature of interface state density in Hf silicate gate dielectrics for CMOS applications x Coulomb limited mobility in Hf silicate based FETs was experimentally quantified by considering the mobility reduction relative to universal mobility values. Using a full quantum mechanical model the mobility limited by Coulomb scattering was calculated considering the physical parameters of the device under study. The calculated and experimentally determined Coulomb limited mobility components were compared using trap charge as the only parameter in the calculation. It was found that a higher trap charge density than determined experimentally was required to match the calculated and measured Coulomb limited mobility in Hf silicate based FETs. The disparity between the theory and the experiment implies that there are other Coulomb scatterers in addition to the interface trap charge. There has been little or no experimental study on the effect of phonons on mobility of Hf silicate based devices, especially, in the ultra thin regime since the first report of successful integration of Hf silicate as a gate dielectric of FETs (A.L.P. Rotondaro, 2002). In this thesis is presented, for the first time, experimental results of phonon-limited mobility in Hf silicate-based FETs by examining the mobility as a function of temperature over a wide range of temperatures below 300 K. Other high-κ based transistors were also studied in order to put the temperature dependence in Hf silicate in perspective. A new model for phonon limited mobility dependence on temperature has been proposed and applied on the experimentally measured data. Compared to the existing model, the new model was found to describe the temperature dependence very well over the entire temperature range studied and over a wide region in the mid-high effective electric field. As stated, scaling introduces difficulties in device characterization. Mobility reduction can not be described by the correct quantity if its evaluation introduces inaccuracies. As such several mobility extraction methods were applied on ultra thin high-κ based FETs to determine the carrier mobility. A comparison of the results (the determined mobility) from all methods showed the disadvantages of each method when applied on high-κ based devices in the ultra thin regime. It was found that the split-CV technique is most xi suitable for (research purposes) studying ultra thin devices – and is thus the preferred method applied throughout the thesis wherever mobility evaluation was required. In all Hf-based dielectrics as this study reveals, have low phonon limited mobility component. Its interface state density was determined to be fairly low compared to the reported values for other high-κ dielectrics and with process refinement, interface charge could be further reduced. Together with a high barrier height, it has already been shown to have a very low gate tunnelling current. All these characteristics make Hf silicate a good alternative to SiO2 in future scaled CMOS applications.

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