We have successfully built and tested an intensity-modulated spectroscopy (IMS) instrument that is centered around a commercial lock-in amplifier, which can be used to perform intensity-modulated spectroscopy (IMS) up to a frequency of 250 kHz. We have tested our instrument on a commercial CdS-based light dependent resistor (LDR), a device with well-known physical properties. We found that the dynamic characterizations results of the CdS-based LDR agree with an already well-established knowledge on its physical properties. We have also performed IMS on a state-of-the-art bulk heterojunction (BHJ) organic photovoltaics (OPV) and introduced a new mode of IMS operation where photovoltaic cells operate under a finite load, including at its maximum power point. From our IMS results on BHJ OPV, we have established IMS at maximum power point as the optimum operating condition for IMS on photovoltaics, a much better alternative to the traditional IMS operation, i.e. intensity-modulated photocurrent spectroscopy (IMPS) and intensity-modulated photovoltage spectroscopy (IMVS). By using IMS under finite load, we have managed to identify a high-frequency feature that was previously invisible under both IMPS and IMVS. We also found that this feature is ageing-related and is more pronounced after long-term storage. We have also managed to find the origin of this aging feature in the diffusion of indium ions that are etched by a PEDOT layer. In addition, with IMS, we are able to determine the BHJ capacitance of a BHJ OPV without absolute calibration of light intensity. We have also performed IMS on a similar BHJ device but with V2O5 as the hole extraction layer. We found that by using V2O5 as a hole extraction layer in OPV, we have avoided the problem of indium ions diffusion into the BHJ. We have also managed to perform IMS on an OLED and able to identify the causes of low-frequency “hook” feature in an OLED IMS results. This feature is attributable to the presence of parallel resistive- and capacitive-like components in the OLED’s emissive layer, which is also caused by the diffusion of indium ions into the OLED’s emissive layer. In addition, by using IMS, we have managed to determine carrier mobility in an OLED, though only an average mobility in the device. Finally, in the aging study of OLED device with IMS, we found that carrier transit time decreases as the device ages.

This thesis addresses the thermal management and reliability concerns of power semiconductor devices from die to system level packaging design. Power electronics is a continuously evolving and challenging field. Systems continue to evolve, demanding increasing functionality within decreasing packaging volume, whilst maintaining stringent reliability requirements. This typically means higher volumetric and gravimetric power densities, which require effective thermal management solutions, to maintain junction temperatures of devices below their maximum and to limit thermally induced stress for the packaging medium. A comparison of thermal performance of Silicon and Silicon Carbide power semiconductor devices mounted on Polycrystalline Diamond (PCD) and Aluminum Nitride (AlN) substrates has been carried out. Detailed simulation and experimental analysis techniques show a 74% reduction in junction to case thermal resistance (Rth (j-c)) can be achieved by replacing the AlN insulating layer with PCD substrate. In order to improve the thermal performance and power density of polycrystalline diamond substrates further at the system level, direct liquid cooling technique of Direct Bonded Copper (DBC) substrates were performed. An empirical model was used to analyse the geometric and thermo-hydraulic dependency upon thermal performance of circular micro pins fins. Results show that micro pin fin direct cooling of DBC can reduce the number of thermal layers in the system, and reduce the thermal resistance by 59% when compared to conventional DBC cooling without a base plate. Thermal management and packaging solutions for the wide band gap semiconductors, such as GaN, is also described in detail. Comparisons of face up and flip chip thermal performance of GaN on Sapphire, Silicon and 6H-SiC substrates in a T0-220 package system is presented. Detailed thermal simulation results analysed using ANSYS® show that a flip chip mounted GaN on sapphire substrate can reduce junction to case thermal resistance by 28% when compared against the face up mounted technique.

Most materials break through the extension of their most prominent crack, as Griffith predicted over a century ago. Despite the fact that the extension of a crack occurs in the nanometre-sized area located at the crack tip end, we still know little about the crucial role that forces play at this scale. With the advent of the Atomic Force Microscopy (AFM), we have been able to apply small calibrated forces at the nanoscale. Until now, AFM has been most successful at unveiling the mechanical properties of biological materials while pulling. Investigating the mechanics of materials while pushing, however, has been less successful. Until now, most indentation experiments were performed at a constant pushing velocity, which precluded measuring the detailed rupture kinetics of the material. In this vein, we have developed an AFM capable of applying a more complex indentation protocol, called force-clamp, which expands the time window of experimentation and allows mapping out the energy landscape of the rupture mechanism. Then, we have investigated the rupture kinetics of an Angstrom-scale simple 2D material – confined solvation layers. By applying force-clamp, we have discovered that the rupture (and reformation) of these solid-like layers occurs through the disruption of a single molecule, contrary to currently accepted mechanical contact models. Secondly, we have investigated the more complex mechanism of lipid membrane rupture, which involves the displacement of tens to hundreds of molecules. In this case, we have developed a pore nucleation model to fit the complex rupture kinetics, which is far from the currently used two-state model. Finally, we have indented whole live cells. As a result, we have measured that lipid membrane lateral interactions ultimately define cell membrane integrity. Altogether, these experiments point out the key role that intermolecular forces play to define the mechanical strength of materials from a fraction of nanometre to several micrometres.

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Networks-on-chip (NoCs) is a communication paradigm that has emerged aiming to address on-chip communication challenges and to satisfy interconnection demands for chip-multiprocessors (CMPs). Nonetheless, there is continuous demand for even higher computational power, which is leading to a relentless downscaling of CMOS technology to enable the integration of many-cores. However, technology downscaling is in favour of the gate nodes over wires in terms of latency and power consumption. Consequently, this has led to the era of many-core processors where power consumption and performance are governed by inter-core communications rather than core computation. Therefore, NoCs need to evolve from being merely metalbased implementations which threaten to be a performance and power bottleneck for many-core efficiency and scalability. To overcome such intensified inter-core communication challenges, this thesis proposes a novel interconnect technology: the surface-wave interconnect (SWI). This new RF-based on-chip interconnect has notable characteristics compared to cutting-edge on-chip interconnects in terms of CMOS compatibility, high speed signal propagation, low power dissipation, and massive signal fan-out. Nonetheless, the realization of the SWI requires investigations at different levels of abstraction, such as the device integration and RF engineering levels. The aim of this thesis is to address the networking and system level challenges and highlight the potential of this interconnect. This should encourage further research at other levels of abstraction. Two specific system-level challenges crucial in future many-core systems are tackled in this study, which are cross-the-chip global communication and one-to-many communication. This thesis makes four major contributions towards this aim. The first is reducing the NoC average-hop count, which would otherwise increase packet-latency exponentially, by proposing a novel hybrid interconnect architecture. This hybrid architecture can not only utilize both regular metal-wire and SWI, but also exploits merits of both bus and NoC architectures in terms of connectivity compared to other general-purpose on-chip interconnect architectures. The second contribution addresses global communication issues by developing a distance-based weighted-round-robin arbitration (DWA) algorithm. This technique prioritizes global communication to be send via SWI short-cuts, which offer more efficient power dissipation and faster across-the-chip signal propagation. Results obtained using a cycleaccurate simulator demonstrate the effectiveness of the proposed system architecture in terms of significant power reduction, considervii able average delay reduction and higher throughput compared to a regular NoC. The third contribution is in handling multicast communications, which are normally associated with traffic overload, hotspots and deadlocks and therefore increase, by an order of magnitude the power consumption and latency. This has been achieved by proposing a novel routing and centralized arbitration schemes that exploits the SWI0s remarkable fan-out features. The evaluation demonstrates drastic improvements in the effectiveness of the proposed architecture in terms of power consumption ( 2-10x) and performance ( 22x) but with negligible hardware overheads ( 2%). The fourth contribution is to further explore multicast contention handling in a flexible decentralized manner, where original techniques such as stretch-multicast and ID-tagging flow control have been developed. A comparison of these techniques shows that the decentralized approach is superior to the centralized approach with low traffic loads, while the latter outperforms the former near and after NoC saturation.