A model of a system is important for applications such as simulation, prediction and control. Closed-loop identification (CLIO) is a means of identifying a process model while the process is still under feedback control. The motivation of this project is to find a way to do closed-loop identification while causing minimum disruption to the controlled process. There are two main categories of closed loop identification. One is closed-loop identification with external excitation (Ljung 1987, System Identification: theory for the user, Englewood Cliffs, NJ: Prentice-Hall). Another is relay identification (A strom and Hagglund I984a, Automatic Tuning of Simple Regulators with Specifications on Phase and Amplitude Margins, Alltomatim, Vo1.20, No.5. pp645-651 ). The first achievement of this thesis is the establishment of a connection between previously unrelated facts by comparing the two main categories of closed loop identification methods. Their advantages and disadvantages were highlighted through case studies. The second. and the main achievement of this thesis is to propose a new closed-loop identification scheme for a single-input-single-output (5IS0) control loop. It is based on a quantizer insel1ed into the feedback path. The novel contribution of this thesis is to bring the closed-loop identitication with external excitatiun method and the relay identification method into a unified framework for the first time. It gives recommendations about the appropriate method to use for a given quantizer interval. When the quantization interval is small, the quantization error is persistently exciting, equivalent to an external excitation. The two-stage (step) method can be applied. When the quantization interval is large. the relay method can be applied instead. Nonlinearity caused by the quantizer is analyzed. which indicates that nonlinearity increases with the quantization interval. Simulations and experiments showed that the proposed closed-loop idclItification schemc based on quantization is successful. The third achievement of this thesis is the implementation. testing and extension of a quantized regression (QR) algorithm that retrieves the underlying information from quantized signals such as those from the analogue to digital converter of a plant instrument. The algorithm is a combination of the 'Gaussian Fit' schcme with expectation-maximization (EM) algorithm. The new QR algorithm can optimally estimate the model parametcrs and recover the underlying signal at the same time for an arbitrary number of quantizer levels.

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This thesis presents a number of digital phase-locked loop architectures, which are based on the Time Delay Digital Tanlock Loop (TDTL) system for improving various performance parameters of the original first- and second-order TDTL loops to alleviate some of their inherent limitations. These limitations include degradation of the linearity and span of the locking range in the first- and second-order loops respectively, and the acquisition speed of the first-order loop. The acquisition speed, the circuit complexity, the locking range and the noise performance of the original TDTL architecture were investigated and new improved architectures are proposed. The design, mathematical analysis, and testing results of the proposed architectures are presented. Evaluation using MATLAB/Simulink. of these architectures, under noisy and noise-free environments demonstrated significant improvements in the above performance parameters compared to the original TDTL system. Further, some of the proposed architectures are re-configurable which means that they can be optimized for a given performance parameter to match a given application requirement. In addition, in order to assess the real-time performance of these architectures, some were implemented using FPGA-based (field programmable gate array) development systems. Practical results obtained from those hardware modules concurred with the results obtained from simulation using MA TLAB/Simulink. Additionally, a number of new digital PLL system topologies for synchronizing a voltage source inverter with the low-voltage utility grid were developed and tested. The systems were tested, using MA TLAB/Simulink, under extreme conditions, such as introducing excessive total harmonic distortion (THD) in the grid voltage waveform. Despite the fact that such distortion can significantly falsify the zero-crossings, the proposed architectures were able to establish synchronization in less than 200 ms. In more realistic situations, locking was achieved within 100 ms. Such systems should find applications for interfacing renewable energy generating systems with the low-voltage utility grid.

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This thesis is focused on the design, analysis, simulation and implementation of new improved architectures of the Time Delay Digital Tanlock Loop (TDTL) based digital phase-locked loop (DPLL). The proposed architectures overcome some fundamental limitations exhibited by the original TDTL. These limitations include the presence of nonlinearity in the phase detector (PD), the non-zero phase error of the first-order loop, the restricted locking range, particularly of the second-order loop, the limited acquisition speed and the noise performance. Two approaches were adopted in this work to alleviate these limitations: the first involved modifying the original TDTL through the incorporation of auxiliary circuit blocks that enhance its performance, whilst the second involved designing new tanlock-based architectures. The proposed architectures, which resulted from the above approaches, were tested under various input signal conditions and their performance was compared with the original TDTL. The proposed architectures demonstrated an improvement of up to fourfold in terms of the acquisition times, twofold in noise performance and a marked enhancement in the linearity and in the locking range. The effectiveness of the proposed tanlock-based architectures was also assessed and demonstrated by using them in various applications, which included FM demodulation, FM threshold extension, FM demodulation with improved THD (total harmonic distortion), and Doppler effect improvement. The results from these applications showed that the performance of the new architectures outperformed the original TDTL. Real-time performance of these architectures was evaluated through implementation of some of them on an FPGA (field-programmable gate array) based system. Practical results from the prototype FPGA based implementations confirmed the simulation results obtained from MATLAB/Simulink.