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Certain unique sights and sounds of video games from the 1980s and 1990s have been codified as a retro game style, celebrated by collectors, historians, and game developers alike. In this report, I argue that this nostalgic celebration has escaped critical scrutiny and in particular omits the diverse experiences of girls and women who may have been alienated by the tough, intimidating nature of a twentieth-century video-game culture that was primarily created by and for boys. Indeed, attempts to attract girls to gaming, such as the 1990s girls' game movement, are usually criticized in or absent from mainstream video-game histories, and girly video games are rarely viewed with the same nostalgic fondness as games like Super Mario Bros. This condition points to a larger cultural practice of trivializing media for girls and, by extension, girlhood and girls themselves. My critical design response to this condition has been twofold. First, I have recuperated and resituated twentieth-century girly games as collectible, valuable, and nostalgic, thereby subverting conventional historical narratives and suggesting that these games have inherent cultural value. Second, I have created new works that reimagine 8-bit style as an expression of nostalgia for twentieth-century girlhood rather than for twentieth-century boyhood. This report contains documentation of some relevant projects I have undertaken, such as the creation of a video-game museum and an 8-bit video game called Electronic Sweet-N Fun Fortune Teller. In these projects and in future works, I hope to disrupt dominant narratives about video game history and nostalgia that continue to marginalize and trivialize girls' and women's experiences and participation in contemporary game cultures. / text

The aim of this thesis study is to develop a simulator for an 8-bit microcontroller and the written document of this thesis study analyses the process of devoloping a software for simulating an 8 bit microcontroller, MC68HC11. In this simulator study a file processing including the parsing of the assembler code and the compilation of the parsed instructions is studied. Also all the instruction execution process containing the cycle and instruction execution and the interrupt routine execution is observed through a graphical user interface. Through this graphical user interface all the registries, address bus and data bus updates can also be observed. C++ programming language is used to implement the application. Object oriented programing techniques are used to provide easy of implementation and template usages.

The motivation behind this work is to target the demand for high-speed medium-resolution ADCs for satellite communication systems. An 8-bit, 12.5GS/s folding-interpolating ADC was designed in 0.25µm, 190GHz SiGe BiCMOS technology from IHP. The ADC consists of a THA, a reference resistor ladder, folding amplifiers, an interpolating resistor string, a comparator array, a digital encoder, a coarse quantizer and a bit synchronizer. Post-layout simulation results of the ADC verify that its performance meets all the required specifications. By comparison to other high-speed ADCs, implemented in SiGe technologies, the present design features the highest sampling rate for 8-bit resolution ADCs to date with a good FOM (12.9pJ/conversion). The THA and the comparator were implemented experimentally and characterized to verify their performance and to ascertain the possibility of implementing the complete ADC. The experimental results meet the expected specifications and indicate that both circuits are suitable for the implementation of the ADC.

The motivation behind this work is to target the demand for high-speed medium-resolution ADCs for satellite communication systems. An 8-bit, 12.5GS/s folding-interpolating ADC was designed in 0.25µm, 190GHz SiGe BiCMOS technology from IHP. The ADC consists of a THA, a reference resistor ladder, folding amplifiers, an interpolating resistor string, a comparator array, a digital encoder, a coarse quantizer and a bit synchronizer. Post-layout simulation results of the ADC verify that its performance meets all the required specifications. By comparison to other high-speed ADCs, implemented in SiGe technologies, the present design features the highest sampling rate for 8-bit resolution ADCs to date with a good FOM (12.9pJ/conversion). The THA and the comparator were implemented experimentally and characterized to verify their performance and to ascertain the possibility of implementing the complete ADC. The experimental results meet the expected specifications and indicate that both circuits are suitable for the implementation of the ADC.

Generating a video signal for ATtiny85 , authoring software worldwide for video game console ATARI2600 on the theme of UAV attacks and their media image - a reinterpretation of using "low res" generated video.

Applying machine learning to various applications has gained significant momentum in recent years. However, the increasing complexity of networks introduces challenges such as a larger memory footprint and decreased throughput. This thesis aims to address these challenges by exploring the use of 8-bit floating-point numbers for machine learning. The numerical accuracy was evaluated empirically by implementing software models of the arithmetic and running experiments on a neural network provided by MediaTek. While the initial findings revealed poor accuracy when performing computations solely with 8-bit floating-point arithmetic, a significant improvement could be achieved by using a higher-precision accumulator register. The hardware cost was evaluated using a synthesis tool by measuring the increase in silicon area and impact on clock frequency after four new vector instructions had been implemented. A large increase in area was measured for the functional blocks, but the hardware cost for interconnect and instruction decoding were negligible. A slight decrease in system clock frequency was observed, although marginally. Ideas that likely could improve the accuracy of inference calculations and decrease the hardware cost are proposed in the section for future work.

The following report describes the pre-production, production, and post-production of the short film, 8.BIT.BROS, designed from its inception to fully exploit the years-developed, cumulative and varied skills of its director. The fantastical narrative focuses on the strained emotional dynamic between two adult brothers that have yet to come to terms with having witnessed their father’s death as children. Their trauma is dramatized and encapsulated in the videogame-themed psychotic hallucinations of the film’s protagonist. The director’s specialized skill-set was put to practical use in both the creation of animatronic creature effect, “Commander Gorgo,” and during the post-production phase of the film, wherein green screen compositing, animation, and motion graphics were used at length to bring the narrative life. / text

This dissertation aims to be a social history of 8-bit computer gaming culture in Czechoslovakia. It focuses mostly on the 1982-1989 period, i.e. from the beginnings of organized computer hobby scene until the end of the so-called "normalization" era. It draws from archival texts, mainly computer club newsletters, and oral history interviews. The resulting corpus is used both to reconstruct the social context surrounding computer game play at the time, and to identify social practices, norms and values connected with computer game playing. Theoretically, the dissertation draws from the social history of media, audience research in the vein of the British cultural studies, and game studies. The dissertation claims that in the earliest days of Czechoslovak computer hobby, the hobbyists were a prime example of active audience. As there was virtually no hardware and software market behind the Iron Curtain, hobbyists had to improvise ways of importing hardware and distributing software, often forming computer clubs to facilitate this. Computer game programming and play were integral parts of hobbyist experimentation. Around 1985, Western commercial games started to enter Czechoslovakia via efficient unauthorized distribution. Computer games have, however, become a hobby of its own a started to spread...

Uttrycket Internet of Things växer sig större och större och världen är på väg att ha 50miljarder uppkopplade enheter till 2020. IoT-enheter är beroende av att ha en låg effektförbrukningoch därför är en processor med låg effektförbrukning viktigt att ha. Denna studieutför tester på två strömsnåla processorer för att komma fram till vilken processor somär mest lämplig till vilken IoT-produkt. Testningen utgick från tre applikationer som i sintur baseras på verkliga IoT-situationer. De tre applikationerna har olika intesitetsnivåer. Iden första applikationen arbetar processorerna inte särskilt hårt, I den andra applikationenfår processorena arbeta mer och i den tredje applikationen får processorerna jobba somhårdast. Effektförbrukningen mäts med hjälp av Atmel Power debugger. Resultatet visaratt IoT-enheter som inte är särskilt aktiva har en lägre effektförbrukning med en 8-bitarsprocessor men en IoT-enhet som är mer aktiv har lägre effektförbrukning med Cortex-M0+baserad 32-bitars processor. / The term Internet of Things grows bigger and bigger and the world is about to have 50 billionconnected devices. IoT devices are dependent on low power consumption and thereforea low power processor is important to have. This study performs tests on two power-savingprocessors to determine which processor is most suitable for an IoT product. The test wasbased on three applications, which in turn are based on actual IoT situations. The threeapplications have different levels of intency. In the first application, the processors do notwork very hard. In the second application, the processors get more work and in the thirdapplication, the processors get the hardest work. Power consumption is measured usingAtmel Power debugger The result shows that low-active IoT devices have a lower powerconsumption with an 8-bit processor, but an IoT device that is more active has lower powerconsumption with a Cortex-M0 + based 32-bit processor.