<p>POTS (Plain Old Telephony Service) systems have traditionally been connected via synchronous connections. When installing new nodes in the telephone network, they may sometimes be connected via packet networks such as Ethernet. Ethernet is an asynchronous network which means that nodes connected to the network don’t have access to the same clock frequency if it is not provided in some other way. If two nodes have different clock frequency, the receiver’s buffer will eventually overflow or starve. While not being a severe problem for telephony, devices used for data transmission, e.g. modems and fax will not be able to function properly. To avoid this it is necessary to synchronize the nodes.</p><p>This thesis investigates methods to synchronize nodes connected over Ethernet by simulating them in Matlab. The simulations show that under certain circumstances it is possible to produce a clock signal conforming to relevant standards.</p>

Complex digital circuits such as microprocessors typically require support circuitry that has traditionally been realized using analog or mixed-signal macros. PLL circuits are used in many integrated applications such as frequency synthesizers and inter-chip communication interfaces. As process technologies advance and grow in complexity, the challenge of maintaining required analog elements and performance for use in circuits such as PLLs grows. Recently, digital PLL (DPLL) has emerged as an alternative to analog PLL to overcome many constraints such as low supply voltage, poor analog transistor behavior, larger area due to integrated capacitor and process variability. However, DPLLs have high deterministic jitter due to quantization noise of time-to-digital converter (TDC) and digitally-controlled oscillator (DCO) and struggle with random jitter of oscillator. In this thesis, hybrid analog/digital proportional/integral control is used to suppress TDC quantization error and digital phase accumulation techniques to mitigate DCO quantization error. VCO phase noise was reduced using an embedded voltage-mode feedback. This feedback loop is implemented by using a switched-C circuit which converts frequency to current. Designed in a 130nm CMOS process, the proposed DPLL generates more than 1GHz output frequency with low input frequency and achieves superior jitter performance compared to conventional DPLL in simulations. / Graduation date: 2013

As Moore���s Law continues to give rise to ever shrinking channel lengths, circuits are becoming more digital and ever increasingly faster. Generating high frequency clocks in such scaled processes is becoming a tough challenge. Digital phase locked loops (DPLLs) are being explored as an alternative to conventional analog PLLs but suffer from issues such as low bandwidth and higher quantization noise. A digital multiplying delay locked loop (DMDLL) is proposed which aims at leveraging the benefit of high bandwidth of DLL while at the same time achieving the frequency multiplication property of PLL. It also offers the benefits of easier portability across process and occupies lesser area. The proposed DMDLL uses a simple flip-flop as 1-bit TDC (Time Digital Converter) for Phase Detector (PD). A digital accumulator acts as integrator for loop filter while a ��-�� DAC in combination with a VCO acts like a DCO. A carefully designed select logic in conjunction with a MUX achieves frequency multiplication. The proposed digital MDLL is taped out in 130nm process and tested to obtain 1.4GHz output frequency with 1.6ps RMS jitter, 17ps peak-to-peak jitter and -50dbC/Hz reference spurs. / Graduation date: 2012

Phase Locked Loops(PLLs) are an integral part of almost every electronic system. Systems involving low frequency clocks often require PLLs with low bandwidth. The area occupied by the large loop filter capacitor and resistor in a low bandwidth PLL design makes the realization of traditional charge-pump PLL architecture impractical on a single die, mandating external components on the board. In order to maintain low loop bandwidth the designer is often forced to choose very low values of charge pump current which can lead to reliability issues. In this work, a semi-digital architecture for very low bandwidth monolithic PLLs is proposed. This architecture eliminates large components in traditional charge-pump PLL, thus allowing the realization of on-chip low bandwidth PLLs. A 2x2mm PLL is realized in 180nm CMOS with 75mHz bandwidth consuming 400μW power from 1.8V supply. The prototype PLL locks to an input clock of 1Hz and generates 20kHz output clock with a measured peak-to-peak jitter of 100ns. / Graduation date: 2013

The objective of this research is to demonstrate the feasibility of the implementation of wideband RF CMOS PLLs with high spectral purity using deep sub-micron technologies. To achieve wide frequency coverage, this dissertation proposed a 45-nm SOI-CMOS RF PLL with a wide frequency range to support multiple standards. The PLL has small parasitic capacitance with the help of a SOI technology, increasing the frequency tuning range of a capacitor bank. A designed and fabricated chip demonstrates the PLL supporting almost all cellular standards with a single PLL. This dissertation also proposed a third order sample-hold loop filter with two MOS switches for high spectral purity. Sample-hold operation improves in-band and out-of-band phase noise performance simultaneously in RF PLLs. By controlling the size of the MOS switches and control time, the nonideal effects of the MOS switches are minimized. The sample-hold loop filter is implemented within a 45-nm RF PLL and the performance is evaluated. Thus, this research provides a solution for wideband CMOS frequency synthesizers for multi-band, multi-mode, and multiple-standard applications in deep sub-micron technologies.

In all energy systems, the parameters necessary to calculate power are the same in functionality: an effort or force needed to create a movement in an object and a flow or rate at which the object moves. Therefore, the power equation can generalized as a function of these two parameters: effort and flow, P = effort * flow. Analyzing various power transfer media this is true for at least three regimes: electrical, mechanical and hydraulic but not for magnetic. This implies that the conventional magnetic system model (the reluctance model) requires modifications in order to be consistent with other energy system models. Even further, performing a comprehensive comparison among the systems, each system's model includes an effort quantity, a flow quantity and three passive elements used to establish the amount of energy that is stored or dissipated as heat. After evaluating each one of them, it was clear that the conventional magnetic model did not follow the same pattern: the reluctance, as analogous to the electric resistance, should be a dissipative element instead it is an energy storage element. Furthermore, the two other elements are not defined. This difference has initiated a reevaluation of the conventional magnetic model. In this dissertation the fundamentals on electromagnetism and magnetic materials that supports the modifications proposed to the magnetic model are presented. Conceptual tests to a case study system were performed in order to figure out the network configuration that better represents its real behavior. Furthermore, analytical and numerical techniques were developed in MATLAB and Simulink in order to validate our model. Finally, the feasibility of a novel concept denominated magnetic transmission line was developed. This concept was introduced as an alternative to transmit power. In this case, the media of transport was a magnetic material. The richness of the power-invariant magnetic model and its similarities with the electric model enlighten us to apply concepts and calculation techniques new to the magnetic regime but common to the electric one, such as, net power, power factor, and efficiency, in order to evaluate the power transmission capabilities of a magnetic system. The fundamental contribution of this research is that it presents an alternative to model magnetic systems using a simpler, more physical approach. As the model is standard to other systems' models it allows the engineer or researcher to perform analogies among systems in order to gather insights and a clearer understanding of magnetic systems which up to now has been very complex and theoretical.

POTS (Plain Old Telephony Service) systems have traditionally been connected via synchronous connections. When installing new nodes in the telephone network, they may sometimes be connected via packet networks such as Ethernet. Ethernet is an asynchronous network which means that nodes connected to the network don’t have access to the same clock frequency if it is not provided in some other way. If two nodes have different clock frequency, the receiver’s buffer will eventually overflow or starve. While not being a severe problem for telephony, devices used for data transmission, e.g. modems and fax will not be able to function properly. To avoid this it is necessary to synchronize the nodes. This thesis investigates methods to synchronize nodes connected over Ethernet by simulating them in Matlab. The simulations show that under certain circumstances it is possible to produce a clock signal conforming to relevant standards.

Mixed-signal designs are becoming more and more complex every day. In order to adapt to the new market requirements, a formal process for design and verification of mixed signal systems i. e. top-down design and bottom-up verification methodology is required. This methodology has already been established for digital design. The goal of this research is to propose a new design methodology for mixed signal systems. In the first two chapters of this thesis, the need for a mixed signal design flow based on top-down design methodology will be discussed. The proposed design flow is based on behavioral modeling of the mixed signal system using one of the mixed signal behavioral modeling languages. These models can be used for design and verification through different steps of the design from system level modeling to final physical design. The other advantage of the proposed flow is analog and digital co-design. In the remaining chapters of this thesis, the proposed design flow was verified by designing an 800 MHz mixed signal PLL. The PLL uses a charge pump phase frequency detector, a single capacitor loop filter, and a feed forward error correction architecture using an active damping control circuit instead of passive resistor in loop filter. The design was done in 0. 18- <i>µ</i> m CMOS process technology.

SMA belongs to a class of so-called “smart materials” which possess properties that can be controlled by application of various types of stimuli – stress, temperature, electric field or magnetic field. In particular, SMA is a smart material which undergoes a temperature- or stress-dependent phase transformation giving it the property of remembering its original shape. Once deformed (up to a certain recoverable strain), SMA returns to its original shape upon heating. In this thesis, a study of SMA models and techniques to improve the performance of SMA actuators was carried out. In general, an SMA model is required for 3 main purposes: simulation, analysis and for model-based hysteresis compensation. In this work, the reduced-order form of John Shaw’s partial-differential equation model is chosen for implementation and simulation. The reduced-order form is used because its simpler structure makes it more useful for real-time control applications. The parameters were estimated for the John Shaw model followed by its implementation in MATLAB. From the view of control applications, a limitation of the John Shaw model is the inability to reproduce the so-called ‘minor loop behavior’ which is observed when the material is subject to cycling resulting in incomplete phase transformations. Modeling minor loop behavior is particularly important in closed-loop strain (or position) control applications since achieving a specific target strain between the two (load-dependent) extremes requires partial phase transformation. Herein, the governing equations are modified to include minor loop behavior. This behavior was tested using damped signals which would be expected to trigger minor loops in the actual SMA and reasonable match is observed from the simulations. The use of SMA actuators is limited by the relatively slow response time compared to other smart materials. The conventional current saturation (CS) scheme limits the maximum current into the wire at the manufacturer-specified safe current values in order to protect the wire from damage due to overheating. However, this is a conservative limit on the maximum current and hence, the response is artificially slowed. In order to improve the response time, a model-based temperature saturation (MBTS) scheme was developed, in which current is saturated based on model-predicted temperature. The MBTS scheme allows much higher currents to be applied to the wire, while ensuring that the wire is not damaged. Based on simulations using the reduced-order John Shaw model, it is observed that better tracking occurs using the MBTS scheme in the actuation scheme as compared to the CS scheme.

In this report, I examine a part of the teaching of computer programming in a Swedish ”gymnasium”, carried out through the course ”Programmering A”. In this beginner course, students, often in heterogeneous groups, are taught the basics of using a programming language. However, quite a few pupils are facing problems in completing the course. Especially, the construction and use of ”for-loops” (in the programming language C++) seems to be hard to master. The report focus on the making and practising of a student-oriented excercise, which uses both visual and problem-oriented means to teach ”for-looping” in a way that makes learning easier, and also stimulates the students' creativity. Pros and cons with this excercise are discussed in the report, within the theoretical framework of the mathematician Papert and his ”constructionism”, as well as with some Swedish constructionist studies. The report is based on a qualitative study of three small student groups performing the excercise, at a ”gymnasium” in Sweden.