Power line communications (PLC) in integrated circuits (ICs) was proposed by Dr. Dong S. Ha's group in 2005. Their goal was to utilize the power distribution network for data communications as well as delivery of power, so that the routing overhead can be avoided and the number of pins in the chip can be reduced. Dr. Ha's group demonstrated through measurements the existence of pass-bands in the power distribution networks and the feasibility of power line communications in ICs. Several PLC receivers were developed to recover data superimposed on the power lines of an IC. This thesis research investigated a new PLC receiver to improve shortcomings of previous PLC receivers, specifically to improve the reliability while reducing power dissipation. The proposed PLC system adopts an amplitude shift keying (ASK) modulation to transmit and detect data through power distribution networks. The proposed PLC receiver consists of three main sub-blocks. The first sub-block is a level shifter, which lowers the offset voltage of the supply voltage to approximately 0.5VDD. The second sub-block is a signal extractor, which detects a data signal superimposed on the power line. The signal extractor is a differential amplifier, in which one input is connected through an RC low-pass filter. The DC voltage of the data signal varies in accordance with the supply voltage fluctuations and droop. The low-pass filter intends to pass only the DC term of the data signal. Since the DC voltage is common for both inputs of the differential amplifier, it is removed from the data signal through the common mode rejection of the differential amplifier. Therefore, the signal extractor can mitigate supply voltage fluctuations and droops. The last sub-block is the logic restorer, which converts the differential signal to a logic value based on a Schmitt trigger. The hysteresis of the Schmitt trigger improves the noise immunity of the receiver The proposed PLC receiver is designed and fabricated in CMOS 0.18 µm technology under the supply voltage of 1.8 V. Measurement results of the three sub-blocks and the entire PLC receiver are presented and compared with simulation results. The data rate for the measurements is set to 10.0 Mbps, and the ASK modulation scheme adopts VDD (= 1.8 V) for logic 0 and 90 mV above VDD for logic 1. The measurements show that the PLC receiver can tolerate the supply voltage drop by 0.423 V or 23.0%. The power dissipation for the receiver is 3.2 mW under 1.8 V supply. The core area of the receiver is 72.2 µm x 74.9 µm. / Master of Science

The objectives of this research work are to investigate, design and implement active integrated antennas comprising active devices connected directly to the patch radiators, for various applications in high efficiency RF front-ends, integrated oscillator antennas, design and optimization of harmonic suppression antennas using a genetic algorithm (GA). A computer-aided design approach to obtain a class F operation to optimizing the optimal fundamental load impedance and designing the input matching circuits for an active integrated antenna of the transmitting type is proposed and a case study of a design for 1.6 GHz is used to confirm the design principle. A study of active integrated oscillator antennas with a series feed back using a pseudomorphic high electronmobility transistor (PHEMT) confirms the design procedure in simulation and measurement for the oscillator circuit connected directly to the active antenna. Subsequently, another design of active oscillator antenna using bipolar junction transistor (BJT) improves the phase noise of the oscillation and in addition to achieve amplitude shift keying (ASK) and amplitude modulation (AM) modulation using the proposed design circuit. Moreover, the possibility of using a sensor patch technique to find the power accepted by the antenna at harmonic frequencies is studied. A novel numerical solution, for designing and optimizing active patch antennas for harmonic suppression using GA in collaboration with numerical electromagnetic computation (NEC), is presented. A new FORTRAN program is developed and used for adaptively meshing any planar antenna structure in terms of wire grid surface structures. The program is subsequently implemented in harmonic suppression antenna design and optimization using GA. The simulation and measurement results for several surface structures show a good agreement.

yes / The objectives of this research work are to investigate, design and implement active integrated antennas comprising active devices connected directly to the patch radiators, for various applications in high efficiency RF front-ends, integrated oscillator antennas, design and optimization of harmonic suppression antennas using a genetic algorithm (GA). A computer-aided design approach to obtain a class F operation to optimizing the optimal fundamental load impedance and designing the input matching circuits for an active integrated antenna of the transmitting type is proposed and a case study of a design for 1.6 GHz is used to confirm the design principle. A study of active integrated oscillator antennas with a series feed back using a pseudomorphic high electronmobility transistor (PHEMT) confirms the design procedure in simulation and measurement for the oscillator circuit connected directly to the active antenna. Subsequently, another design of active oscillator antenna using bipolar junction transistor (BJT) improves the phase noise of the oscillation and in addition to achieve amplitude shift keying (ASK) and amplitude modulation (AM) modulation using the proposed design circuit. Moreover, the possibility of using a sensor patch technique to find the power accepted by the antenna at harmonic frequencies is studied. A novel numerical solution, for designing and optimizing active patch antennas for harmonic suppression using GA in collaboration with numerical electromagnetic computation (NEC), is presented. A new FORTRAN program is developed and used for adaptively meshing any planar antenna structure in terms of wire grid surface structures. The program is subsequently implemented in harmonic suppression antenna design and optimization using GA. The simulation and measurement results for several surface structures show a good agreement.

[pt] Neste trabalho realizamos uma prova da viabilidade de um sistema de comunicação óptica com capacidade de transmissão de 50 Gbit/s em uma largura de banda de 50 GHz utilizando o legado dos sistemas com taxas de 10 Gbit/s. Uma série de configurações experimentais foi testada em uma ordem de complexidade crescente para verificar separadamente as etapas e as técnicas aplicadas para o aumento da capacidade de transmissão de dados e a eficiência espectral. Em alguns casos, a curva característica resultante da configuração backto- back do analisador de taxa de erro de bit média foi utilizada como referência para comparação das configurações experimentais realizadas durante o trabalho. / [en] In this work we perform a proof of feasibility of 50 Gbit/s transmission within a 50 GHz optical bandwidth exploring the 10 Gbit/s legacy. A series of experimental configurations were tested in an order of increasing complexity to verify separately the steps and applied techniques for increasing data transmission capacity and spectral efficiency. In some cases, the comparison of experimental configuration was made using the back-to-back configuration of the Bit Error Rate Tester.