The first topic of this thesis is a C-less and R-less ASK (Amplitude Shift Keying) demodulator design for wireless implantable devices. Lots of prior ASK demodulators were composed of one or more capacitors which might be integrated in a chip or positioned off-chip on a PCB (Printed Circuit Board). The capacitor increases the area of the implantable system regardless of on-chip or off-chip, which violates the small-scale requirement for implanted applications. Thus, this work proposes a miniature ASK demodulator without any passive elements, i.e., R or C. The noise margin of the envelope detector in the C-less ASK demodulator is enlarged such that any Schmitt trigger or current limiting resistor is no longer needed. It results in the number of transistors required for the ASK demodulator circuit is reduced to 12. The second topic of this thesis is a design of a low-power 2-dimensional bypassing multiplier. The proposed bypassing cells constituting the multiplier skip redundant signal transitions when the horizontally (row) partial product or the vertically (column) operand is zero. Thorough post-layout simulations show that the power dissipation of the proposed design is reduced by more than 41% compared to the prior design with obscure penalty of delay and area.

This thesis includes two topics, which are a Self-sampled ALL-MOS ASK Demodulator and a Synchronous DAC with Self-calibration. An all-MOS ASK demodulator with a wide bandwidth for lower ISM band applications is presented in the first half of this thesis. The chip area is reduced without using any passive element. It is very compact to be integrated in an SOC (system-on-chip) for wireless biomedical applications, particularly in biomedical implants. Because of low area cost and low power consumption, the proposed design is also easily to be integrated in other mobile medical devices. The self-sampled loop with a MOS equivalent capacitor compensation mechanism enlarges the bandwidth, which is more than enough to be adopted in any application using lower ISM bands. To demonstrate this technique, an ASK demodulator prototype is implemented and measured using a TSMC 0.35 £gm standard CMOS process. The second topic reveals a synchronous DAC with self-calibration. The main idea is to use a calibration circuit to overcome large error of output voltage caused by the variation of the unit capacitor. When DAC is not calibrated, INL is larger than 1.7 LSB. After calibrated, INL is improved to be smaller than 0.5 LSB. To demonstrate this technique, a DAC prototype is implemented and measured using a TSMC 0.18 £gm standard CMOS process.

The thesis is composed of two topics: A SOC design for one-time implantable spinal cord stimulation system ¡]SCS¡^, and the design of an inter-chip capacitance coupling circuit. In the first topic, the SOC design using wireless power and data transmission techniques for the SCS system is presented in this work. The proposed SOC can control 4 electrodes to generate different patterns of stimulation waves. It has multiple modes to drive whole the SCS system. Notably, the SOC contains a novel ASK demodulator which converts the ASK signals into digital signals reliably. The SOC is implemented using a typical 0.18-£gm 1P6M CMOS process. The chip area is only 1.71 * 1.41 mm2. Besides, the volume of the implantable SCS pulse generator utilizing this SOC is less than 24 cm3, and the power consumption is only 59.4 mW. In the second topic, a high-speed inter-chip capacitance coupling circuit is presented. Digital signals between two chips can be transceived through capacitive coupling of the proposed circuit. Notably, the transceivers are designed below the capacitors to attain the area reduction. It is an advanced application for high-speed wafer testing and 3D IC communication. A prototype chip is presented to achieve 2 Gbps on silicon using a typical 0.18 £gm 1P6M CMOS process. The chip area is 1045 ¡Ñ 894 £gm2. Besides, it only costs 21.47 mW in terms of power consumption. This capacitive coupling technique for high-speed digital circuit has great potential in the coming future.