Globally-asynchronous locally-synchronous (GALS) systems may become a solution for nowadays challenges in the field of VLSI design. Fully synchronous chips are becoming not feasible anymore due to clock distribution and power consumtion problems. The value of GALS lies in combination of well know synchronous design methods and relative simple asynchronous communication channels. The key components are the communication control ports around the synchronous modules and the stretchable clock also called a wrapper. This clock has a unbound delay and is controlled by events the asynchronous channel. A simple GALS system consisting of a 4-bit transmitter, integrator and receiver has been designed and layouted for a 0,35 micron CMOS proces. A 4-phase bundled protocol is used with GasP FIFO's. Novel circuits has been designed to switch from the one wire asynchronous communication of the FIFO to the 4-phase of the wrapper. The report also dicusses the challenges for manufature test on asynchronous designs. A test strategy for GALS systems is been devoloped.

Heat, clock scew and frequency optimization are some of the problems a semiconductor designer must face. By splitting a synchrounous block into multiple pieces which comunicates asynchronously with eachother and provide them with independent clocks, these problems may be reduced. GALS (Global Asynchronous Local Synchronous) is a wrapper that wraps a synchronous block and provides it with a clock. Multiple GALS-elements will make the whole system. The clockfrequency may be independently adjusted between each block. The clocks may be started and halted independantly depending on the workload. Describing the system in a hardware language as VHDL, and implement it into an FPGA (Field Programmable Grid Array), makes the development of applications fast and cheap.

In the multi-core systems, the data transfer between cores becomes a major challenge. The on-chip interconnect networks should be low latency, high throughput, scalability, better router or arbitration strategy, and low power consumption. An asynchronous ring bus, which is 33 bit width, adopting dual-rail single-track data protocol is proposed in this thesis. It provides not only robust but also high-speed asynchronous circuits condition. Owing to asynchronous circuits design, there are different transfer times in different hop counts. The shorter the distance is, the faster the data can be transferred. Unlink the synchronous ring bus, the bus frequency must be limited by the longest hop count latency. On the other hand, the transmission time of asynchronous circuits will not be held up by the longest distance even though the number of core is increased. For providing higher throughput, multiple cores which are able to access the bus simultaneously make a direct connection between each other. In bus arbitration, distribution arbiter is adopted to arbitrate the right to use the bus and solve the collision. Finally, the system performance in different arbitration strategies has been estimated in TSMC 0.18£gm process in this thesis. The transmission time of the shortest distance is 1.5 ns approximately, and the longest distance first has a better performance in different arbitration strategies.

Dr. Paul V. Gratz Network-on-Chip (NoC) designs have emerged as a replacement for traditional shared-bus designs for on-chip communications. As with all current VLSI design, however, reducing power consumption in NoCs is a critical challenge. One approach to reduce power is to dynamically scale the voltage and frequency of each network node or groups of nodes (DVFS). Another approach to reduce power consumption is to replace the balanced clock tree with a globally-asynchronous, locally-synchronous (GALS) clocking scheme. NoCs implemented with either of these schemes, however, tend to have high latencies as packets must be synchronized at the intermediate nodes between source and destination. In this work, we propose a novel router microarchitecture which offers superior performance versus typical synchroniz- ing router designs. Our approach features Asynchronous Bypass Channels (ABCs) at intermediate nodes thus avoiding synchronization delay. We also propose a new network topology and routing algorithm that leverage the advantages of the bypass channel offered by our router design. Our experiments show that our design improves the performance of a conventional synchronizing design with similar resources by up to 26 percent at low loads and increases saturation throughput by up to 50 percent.

Due to the impressive capabilities of human visual processing, interactive visualization methods have become essential tools for scientists to explore and analyze large, complex datasets. However, traditional approaches do not account for the increased size or latency of data retrieval when interacting with these often remote datasets. In this dissertation, I discuss two novel design paradigms, based on accepted models of the information visualization process and graphics hardware pipeline, that are appropriate for interactive visualization of large remote datasets. In particular, I discuss novel solutions aimed at improving the performance of interactive visualization systems when working with large numeric datasets and large terrain (elevation and imagery) datasets by using data reduction and asynchronous retrieval of view-prioritized data, respectively. First I present a modified version of the standard information visualization model that accounts for the challenges presented by interacting with large, remote datasets. I also provide the details of a software framework implemented using this model and discuss several different visualization applications developed within this framework. Next I present a novel technique for leveraging the hardware graphics pipeline to provide asynchronous, view-prioritized data retrieval to support interactive visualization of remote terrain data. I provide the results of statistical analysis of performance metrics to demonstrate the effectiveness of this approach. Finally I present the details of two novel visualization techniques, and the results of evaluating these systems using controlled user studies and expert evaluation. The results of these qualitative and quantitative evaluation mechanisms demonstrate improved visual analysis task performance for large numeric datasets.

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<p>Globally-asynchronous locally-synchronous (GALS) systems may become a solution for nowadays challenges in the field of VLSI design. Fully synchronous chips are becoming not feasible anymore due to clock distribution and power consumtion problems. The value of GALS lies in combination of well know synchronous design methods and relative simple asynchronous communication channels. </p><p>The key components are the communication control ports around the synchronous modules and the stretchable clock also called a wrapper. This clock has a unbound delay and is controlled by events the asynchronous channel. </p><p>A simple GALS system consisting of a 4-bit transmitter, integrator and receiver has been designed and layouted for a 0,35 micron CMOS proces. A 4-phase bundled protocol is used with GasP FIFO's. Novel circuits has been designed to switch from the one wire asynchronous communication of the FIFO to the 4-phase of the wrapper. </p><p>The report also dicusses the challenges for manufature test on asynchronous designs. A test strategy for GALS systems is been devoloped.</p>

ITC/USA 2013 Conference Proceedings / The Forty-Ninth Annual International Telemetering Conference and Technical Exhibition / October 21-24, 2013 / Bally's Hotel & Convention Center, Las Vegas, NV / Since both airborne and ground applications are able to handle and process IRIG 106, Chapter 10 standard data (further referred to as C10) from files or from live streaming UDP network data, it is a logical extension of the standard to telemeter network data from the air to the ground support systems with little or no modification. This paper describes a method to transport C10 compliant packets over a Class II, telemetry stream (C10 TMDL) which is fully compatible with existing encryptors, transmitters, receivers, and decryptors.

M. Tech. Electrical Engineering. / In the recent past, there has been an increase in demand for high data rate services and system designers are always looking for ways to improve the capacity and quality of service (QoS) of wireless communication networks. The main objective of the study is to propose an asynchronous power allocation scheme based on the classical waterfilling algorithms in a multi-user MIMO uplink system. The proposed algorithm is fully distributed and eliminates the need for user synchronization during power allocation. Each user in the system competes with one another in choosing the capacity maximizing transmit power while treating the multi-user interference as noise. The problem is reduced to finding the optimal transmit covariance matrix of the users that maximizes the sum capacity of the system. We formulate the power allocation problem as a non-cooperative game and show the existence and uniqueness of the Nash Equilibrium (NE) point. The proposed Semi-Asynchronous MIMO Waterfilling algorithm maximizes the system sum capacity without the need for synchronization among users when updating their power allocation.

The analysis of linear motor magnetic properties and application of several linear motor models at work have been performed in consideration of its constructional speciality. The mathematical model of linear motor have been composed on programme QuickField. Varying parameters of linear motor (elements position, materials proportion of motors elements, thickness of secondary element, its position on air gap symmetry) have been maked magnetic properties, specific for several model of linear motor. The teoretical part represent generalized review of linear motors and description of its characteristics. The features of linear motors have been analysed here. The investigation part involving the creation of several linear motor models and analysis of magnetic properties on programme QuickField. This discribing geometric models creation, its parameters setting and making results for several models of linear motors. The programme displaying results in grafic, color map, vector and tables shapes. The results have been analysed and summarized. Finally the conclusions of investigation of linear motor have been formulated: efficiency, operating conditions, application of linear motors are conditioned by constructional speciality of several linear motor. The results of investigation can be used for rational and optimal realization of linear motors in various technological systems.