This work deals with design of communication protocol for data transmission between control computer and computing cores implemented on FPGA chips. The purpose of the communication is speeding the performance demanding software algorithms of non-stream data processing by their hardware computation on accelerating system. The work defines a terminology used for protocol design and analyses current solutions of given issue. After that the work designs structure of the accelerating system and communication protocol. In the main part the work describes the implementation of the protocol in VHDL language and the simulation of implemented modules. At the end of the work the aplication of designed solution is presented along with possible extension of this work.

This thesis deals with Burrows-Wheeler transform (BWT) and possibilities of acceleration of this transform on graphics processing unit (GPU). Methods of compression based on BWT are introduced, as well as software libraries CUDA and OpenCL for writing programs for GPU. Parallel variants of BWT are implemented, as well as following steps necessary for compression, using CUDA library. Amount of compression of used approaches are tested and parallel versions are compared to their sequential counterparts.

This diploma thesis Analysis of selected manoeuvres of bicyclists deals with the history and development of the bicycles, further their division of, construction, analysis accident and national legislation in the theoretical part. The practical part of the master thesis is devoted to the measurements of the bicycles. Specifically, it is about acceleration, deceleration, transverse movement, ride in the curve and looking back before changing the direction. For measuring are selected different type of bikes with different construction. The results of individual measurements are evaluated in the end of the diploma thesis.

This thesis deals with the design of hardware unit used for acceleration of the process of securing network traffic within Lawful Interception System developed as a part of Sec6Net project. First aim of the thesis is the analysis of available security mechanisms commonly used for securing network traffic. Based on this analysis, SSH protocol is chosen as the most suitable mechanism for the target system. Next, the thesis aims at introduction of possible variations of acceleration unit for SSH protocol. In addition, the thesis presents a detailed design description and implementation of the unit variation based on AES-GCM algorithm, which provides confidentiality, integrity and authentication of transmitted data. The implemented acceleration unit reaches maximum throughput of 2,4 Gbps.

Cílem této práce je návrh nové techniky pro stabilizaci obrazu za pomoci hardwarové akcelerace prostřednictvím GPGPU. Využití této techniky umožnuje stabilizaci videosekvencí v reálném čase i pro video ve vysokém rozlišení. Toho je zapotřebí pro ulehčení dalšího zpracování v počítačovém vidění nebo v armádních aplikacích. Z důvodu existence vícerých programovacích modelů pro GPGPU je navrhnutý stabilizační algoritmus implementován ve třech nejpoužívanějších z nich. Jejich výkon a výsledky jsou následně porovnány a diskutovány.

This thesis deals with an echo state network and with acceleration of its learning by implementing the echo state network on a graphics processor. The theoretical part consists of the description of neural networks and some selected types of neural networks, on which is based the echo state network. After that, there are some other algorithms described used for time series analysis and last but not least, the tools that were used in the practical part of the thesis were briefly described. The practical part describes the creation of the accelerated version of the echo state network. After that, there is described the creation of input data sets of real financial indexes, on which the echo state network and the other algorithmns were then tested. By analyzing this accelerated version it was found that its learning speed did not reach the theoretical expectations. The accelerated version works slower, but with greater precision. By analyzing the results of the measurement of the other algorithmns it was found that the highest precision is achieved by solutions based on the neural network principle.

This master’s thesis deals with functional magnetic resonance and monitoring of the effect of acquisition acceleration methods on the quality of functional images and observed BOLD signal. The basic principles of magnetic resonance imaging, the explanation of the specifics of functional magnetic resonance and the formation and scanning of BOLD signal are described here. Subsequently, there is the definition of fMRI experiment and description of sequences used for fMRI, focusing on aquisition acceleration techniques. The influence of sequence parameters on image quality and the data processing methods are explained aftewards. The practical part describes the parameters of used sequences, the acquisition procedure and the task for the subject during aquisition. Data from 26 healthy volunteers were obtained and analyzed afterwards. Based on this, the differencesbetween the different sequence variants were evaluated and the initial assumption that the multi-echo acquisition yields better results with faster measurements than single-echo was confirmed.

This thesis is focused on finding procedures that would accelerate symbolic regressions in Cartesian Genetic Programming. It describes Cartesian Genetic Programming and its use in the task of symbolic regression. It deals with the SIMD architecture and the SSE and AVX instruction set. Several optimizations that lead to a significant acceleration of evolution in Cartesian Genetic Programming are presented. A method of a bit-level parallel simulation that uses AVX2 vectors allows to process 256 input combinations of a logic circuit in paralell. Similarly it is possible to use a byte-level parallel simulation and work with 32 bytes when evolving an image filter. A new method of batch mutation can accelerate the evolution of combinational logic circuits thousand times depending on the problem size. For example, using a combination of these and other methods the evolution of 5 x 5b multipliers took 5.8 seconds on average on an Intel Core i5-4590 processor.

The goal of this project is to design a hardware unit that is designed to accelerate evolutionary design of digital circuits on transistor level. The project is divided to two parts. The first one describes design methods of the MOSFET circuits and issues of evolutionary algorithms. It also analyses current results in this domain and provides a new method for the design and optimization. The second part describes proposed unit that accelerates the new method on the circuit Zynq which integrates ARM processor and programmable logic. The new method functionality has been empirically analysed in the task of optimization of few circuits with more inputs. The hardware unit has been tested for designing of gates on transistor level.

This thesis analyses driving dynamics of tractors and its dependence on their weight and age. In the beginning, brief history of tractor development and definition of basic concept of the tractor analysis is described. The thesis states procedures for obtaining magnitudes necessary for determining of driving dynamics. Experimental part describes the realized measurement on chosen sample of tractors and interprets measured values. Last part of the thesis contains evaluation of the measurement results.