This thesis aims to explore possible implementations and optimizations of the lattice-Boltzmann method. This method allows modeling of fluid flow using a simulation of fictive particles. The thesis focuses on possible improvements of the existing tool HemeLB which  is designed and optimized for bloodflow modeling. Several vectorization and paralellization approaches that could be included in this tool are explored. An application focused on comparing chosen algorithms including optimizations for the lattice-Boltzmann method was implemented as a part of the thesis. A group of tests focused on comparing this algorithms according to performance, cache usage and overall memory usage was performed. The best performance achieved was 150 millions of lattice site updates per second.

This master's thesis deals with the design and implementation of an algorithm for high-speed network packet filtering. The main goal was to provide hardware architecture, which would support large rule sets and could be used in 100 Gbps networks. The system has been designed with respect to the implementation on an FPGA card and time-space complexity trade-off. Properties of the system have been evaluated using various available rule sets. Due to the highly optimized and deep pipelined architecture it was possible to reach high working frequency (above 220 MHz) together with considerable memory reduction (on average about 72% for compared algorithms). It is also possible to efficiently store up to five thousands of filtering rules on an FPGA with only 8% of on-chip memory utilization. The architecture allows high-speed network packet filtering at wire-speed of 100 Gbps.

Tato práce se zabývá Houghovou transformací (HT). HT je nejčastěji používána pro detekci přímek nebo křivek, ale byla zobecněna i pro detekci libovolných tvarů. Hlavní téma této práce jsou parametrizace přímek, speciálně PTLM - zobrazení bodů na přímky. Tyto parametrizace mají tu vlastnost, že bodům v obrázku odpovídají přímky v parametrickém prostoru. Tato práce poskytuje důkazy některých vlastností PTLM. Za zmínku stojí existence páru PTLM vhodného pro detekci a efekt konvoluce v obrázku na obsah parametrického prostoru. V práci jsou prezentovány dvě implementace HT. Obě využívají k akceleraci grafický hardware. Jedna využívá GPGPU API CUDA a druhá zobrazovací API OpenGL. Jako aplikace detekce přímek je uvedena část detekce šachovnicových markerů použitelných pro rozšířenou realitu.

Tato disertační práce se zabývá návrhem nového způsobu softwarově řízené (definované) hardwarové akcelerace pro moderní vysokorychlostní počítačové sítě. Hlavním cílem práce je formulace obecného, flexibilního a jednoduše použitelného konceptu akcelerace použitelného pro různé bezpečnostní a monitorovací aplikace, který by umožnil jejich reálné nasazení ve 100 Gb/s a rychlejších sítích. Disertační práce začíná rozborem aktuálního stavu poznání v oborech síťového monitorování, bezpečnosti a způsobů akcelerace zpracování vysokorychlostních síťových dat. Na základě tohoto rozboru je formulován a navržen zcela nový koncept s názvem Softwarově definované monitorování (SDM). Klíčová funkcionalita uvedeného konceptu je postavená na hardwarově akcelerované, aplikačně specifické (řízené), na tocích založené, informované redukci a distribuci zachycených síťových dat. Toto je zajištěno spojením vysokorychlostního hardwarového zpracování s flexibilním softwarovým řízením, které tak společně umožňují jednoduchou tvorbu různých komplexních a vysoce výkonných síťových aplikací. Pokročilé optimalizace a vylepšení základního SDM konceptu a jeho vybraných komponent jsou v práci též zkoumány, což vede k návrhu zcela unikátní a obecně použitelné FPGA architektury modulárního analyzátoru hlaviček paketů a vysoce výkonného klasifikátoru paketů založeného na kukaččím hashovaní. Nakonec je vytvořen vysokorychlostní SDM prototyp postavený nad FPGA akcelerační síťovou kartou, který je podrobně ověřen v podmínkách nasazení do reálných sítí. Jsou změřeny a diskutovány dosažitelné zlepšení výkonností v několika vybraných monitorovacích a bezpečnostních případech užití. Vytvořený SDM prototyp je rovněž nasazen v produkčním monitorování reálné páteřní sítě sdružení Cesnet a byl komercializován společností Netcope Technologies.

Title: Myodynamics of the support phase during different take-off tasks in human locomotion Objectives: Six types of take-off movement were analyzed in terms of support limb kinematics, take-off dynamics and muscle activation, in order to identify differences in motor control. Methods: 14 male athletes (22.6 ± 4.4 years; 182.4 ± 5.3 cm; 74.7 ± 6.2 kg) took part in laboratory experiment. Each athlete performed six different take-off movements (running, acceleration - first and second step, long jump take-off, high jump take-off and take-off to the hurdle). System Qualisys was used to analyze kinematics of the support limb. Dynamic of the suport phase was measured with Kistler 9281 EA force- plate. ME6000 apparatus was used to measure the muscle activation. Results were processed and statistically evaluated in Matlab (MathWorks, Inc) environment. Pair ANOVA, T-test and Friedmann test were performed to identify differences between take-off movements. regression analysis was introduced to find the relationship between parameters. Results: Significant differences in take-off dynamics are realized with not so significant differences in kinematic and electromyographic parameters. high jump and long jump take-offs acted most specifically in comparison with other types of take-offs. Two typically...

The NetCOPE framework has proven itself as a viable framework for rapid development of hardware accelerated wire-speed network applications using Network Functions Virtualization (NFV). To meet the current and future requirements of such applications the NetCOPE platform has to catch up with upcoming 400 Gigabit Ethernet. Otherwise, it may become deprecated in following years. Catching up with 400 Gigabit Ethernet brings many challenges bringing necessity of completely different way of thinking. Multiple network packets have to be processed each clock cycle requiring a new concept of processing. Advanced memory management is used to ensure constant memory complexity with respect to the number of DMA channels without any impact on performance. Thanks to that, even more than 256 completely independent DMA channels are feasible with current technology. A lot of effort was made to create the framework as generic as possible allowing deployment of 400 Gigabit Ethernet and beyond. Emphasis is put on communication between the framework and host computer via PCI Express technology. Multiple Ethernet ports are also considered. The proposed system is prepared to be deployed on the family of COMBO cards, used as a reference platform.

Thesis is aimed at the possibility of utilization of extreme learning machines and echo state networks for time series forecasting with possibility of utilizing GPU acceleration. Such predictions are part of nearly everyone’s daily lives through utilization in weather forecasting, prediction of regular and stock market, power consumption predictions and many more. Thesis is meant to familiarize reader firstly with theoretical basis of extreme learning machines and echo state networks, taking advantage of randomly generating majority of neural networks parameters and avoiding iterative processes. Secondly thesis demonstrates use of programing tools, such as ND4J and CUDA toolkit, to create very own programs. Finally, prediction capability and convenience of GPU acceleration is tested.

This diploma thesis deals with theoretical analysis, design and practical solution of flight statements electronic sensor. This device is primarily intended for measuring telemetry data during aerobatic flights. Theoretical part contains fundamentals of GPS and inertial navigation systems. Design of the device is divided into three parts - design of block structure, construction and software for the measuring device. The final realization is made with respect to minimal system requirements and to possible future extensibility for wider usage spectrum.

Thesis deals with discrete optimization problems. It focusses on faster ways to find good solutions by means of heuristics and parallel processing. Based on ant colony optimization (ACO) algorithm coupled with k-optimization local search approach, it aims at massively parallel computing on graphics processors provided by Nvidia CUDA platform. Well-known travelling salesman problem (TSP) is used as a case study. Solution is based on dividing task into subproblems using tour-based partitioning, parallel processing of distinct parts and their consecutive recombination. Provided parallel code can perform computation more than seventeen times faster than the sequential version.

This master's thesis describes ways of signal processing via digital devices. Major field of interest is an analysis of Doppler radar response and then mining of informations about detected object (e.g. speed, movement direction, length, ...). There was realized too little research, that's why borrowing some procedures from different branches not too much related to the IT is necessary. In case of using very complex methods that are easy to parallel, hardware implementation on the FPGA is supposed. With transceiver there is created a very powerful on-line system able to process most of tasks real-time. Then processed and transformed data are sent to the output so visualization and display can be made.