A low voltage and low power switch mode power amplifier is proposed. It is designed using TSMC 0.35£gm 2p4m CMOS process technology. It can be applied to hearing aids, and the supply voltage is 1.5V. Experimental results show that the proposed amplifier has the total harmonic distortion (THD) of 0.094% and power efficiency around 79.6%. The proposed power amplifier has superior performance in THD and power efficiency, and it is suitable for low-power low-voltage applications.

Two kinds of low distortion switching power amplifiers are presented in this thesis. In the first power amplifier, we use feedback and low voltage low power circuits to improve the distortion and power efficiency. In the second power amplifier, we use ring oscillator and Noise shaping to construct the circuit and filters are added in the feedback loop to reduce the quantization noise. HSPICE simulations and experimental results verify the proposed circuits. Experimental results show that the THDs of both circuits are all lower than 0.27% at 1.5V supply voltage. This result shows that the proposed power amplifiers have superior performance in THD, and these circuits are applicable to low-distortion, high-efficiency, and low-voltage applications, such as the hearing instruments.

Abstract A simple negative transimpedance amplifier is proposed. Because of inherent low input and output impedance, the frequency response is higher than that of the traditional operational amplifier. Using feedback, the operation frequency of amplifier can be extended. By using a simple feedback resistance, the amplifier¡¦s output level is stabilized without using common-mode feedback. The negative transimpedance amplifier as a common active element is versatile. The characteristics of these application circuits are dominated by the passive elements of the circuits. In the transimpedance-C bandpass filter and transimpedance-C lowpass filter, the , , and Q factor can be tuned. Owing to the negligible loading effect of the transimpedance amplifier, the single stage Rm-C biquad can be cascaded to high order filters. In the voltage controlled oscillator, the oscillation frequency can also be tuned.

Abstract In this research, we intend to develop a sinusoidal VCO with low harmonic distortion. A new sinusoidal VCO is developed with only two OTAs. The number of OTAs is fewer than that previously presented in other papers. The oscillator will be easy to debug and the complexity of the oscillator can be reduced. An AGC control mechanism is applied to the VCO to control the oscillation amplitude and to reduce the harmonic distortion. The oscillation is designed with the frequency around 100MHz and the oscillation amplitude is around 100mV. The simulation results and the problem encountered are discussed.

In this thesis, we investigate the OTDR on-line monitoring feasibility of forward- and backward-pumping distributed Raman fiber amplifiers (FRAs) transmission systems with different OTDR probe lights. In the experiments, we choose the large effect area fiber ( LEAF ) with 50 km long as gain medium of Raman amplifiers. Two different OTDR probe lights with 1.31£gm and 1.65£gm wavelengths are separately used for on-line monitoring forward- and backward-pumping distributed FRAs. We find that the OTDR probe lights affect the optical gain of the 1.55 mm data signal. In the experiments, for the forward-pumping scheme using 1.3£gm OTDR probe light on-line monitor, the optical gain of the 1.55 mm data signal increases 0.2 dB, but for the backward-pumping scheme, that only increases 0.1 dB. In the forward-pumping scheme using 1.65£gm OTDR probe light on-line monitor, the optical gain of the 1.55 mm data signal decreases 0.6 dB, but for the backward-pumping scheme, that only decreases 0.2 dB. We also find the OTDR on-line monitoring distribution fiber Raman amplifiers Systems makes OTDR traces distortion. In an aspect of system BER performance, the system power penalty on account of the OTDR monitoring in both 10 Gb/s forward- and backward-pumping schemes is trivial¡@. In the forward-pumping scheme using 1.3£gm OTDR probe light on-line monitor, the power penalty is about 0.1 dB, but for the backward-pumping scheme that is about 0.05 dB. As the forward-pumping scheme using 1.65£gm OTDR probe light, the power penalty is about 0.2 dB, but for the backward-pumping scheme that is about 0.07 dB.

The need of the everyday user to transfer large amounts of data is driving the need for larger data transfer capacity. Optical communication networks can satisfy this need. To be economically viable, optical transceivers must be integrated onto chips at low cost, using relatively cheap semiconductor processes. The optical preamplifier (transimpedance amplifier) receives optical information and converts it to a useful electrical form. It must operate at high speed, contribute little distortion to the input signal, and add little electrical noise to the incoming signal. This thesis investigates the design techniques in the literature, and proposes new architectures. Two high performance preamplifiers are designed, one using GaAs HEMTs, and the other using GaAs HBTs, each with different circuit techniques. The HEMT preamplifier has a transimpedance gain of 1.4 kΩ, the highest in the literature for 10 Gb/s operation, along with a low input referred noise current of about 15 pA/Hz1/2 at a bandwidth of 6.3 GHz. The HBT preamplifier also has a transimpedance gain of 1.5 kΩ, with a low input referred noise current of about 7 pA/Hz1/2. Both have clear, open eye-diagrams with a 10 Gb/s bit stream input, and are suitable for integration on a chip. The HEMT preamplifier was implemented as a common-gate, common-source amplifier cascade with a darlington output driver for a 50 Ω load. The HBT preamplifier was implemented as common-emitter darlington amplifier with shunt peaking, and a simple emitter degenerated output driver for a 50 Ω load. Both implementations exceeded the bandwidth, transimpedance gain and noise performance typically expected of the transistor technologies used. It is shown that the transimpedance limit can be circumvented by the use of novel architectures and shunt peaking.

Performance and power of sense amplifiers have big implications on the speed of caches used in microprocessors as well as power consumption of IPs in low power system on chips. The speed of voltage sense amplifiers are limited by the differential voltage development time on high capacitance SRAM bit-lines. The dynamic power increases with the differential voltage that needs to be developed on the bit-lines. This report explores multiple sense amplifier techniques - in addition to the conventional voltage sense amplifier, it analyzes current sense amplifier, charge transfer sense amplifier as wells as current latched sense amplifier and compares them in speed, area and power consumption to the voltage sense amplifier. A current sense amplifier operates by sensing the bit cell current directly and shows power and area advantages. A charge transfer sense amplifier makes use of charge redistribution between the high capacitance bit-lines and low capacitance sense amplifier output nodes to provide power benefits. This report also explores the design of a six transistor SRAM bit cell. All circuits are designed and simulated on a 45nm CMOS process. / text

Electrical signals produced in the human body can be used for medical diagnosis and research, treatment of diseases, pilot safety etc. These signals are extracted using an electrode (or transducer) to convert the ion current in the body to electron current. After the electrode, the very low amplitude extracted signal is amplified by an analog frontend that typically consists of an instrumentation amplifier (IA), a programmable gain amplifier (PGA), and a low pass filter (LPF). The output of the analog frontend is converted to digital signal by an analog to digital converter (ADC) for subsequent processing in the digital domain. This thesis discusses the circuit design challenges of the analog frontend instrumentation amplifier, compares existing circuit topologies used to implement the IA and proposes a new frontend IA. The proposed circuit uses the Current Balancing Instrumentation Amplifier (CBIA) topology to achieve high gain accuracy over a wide range of the output impedance. In addition it uses common circuit design techniques such as chopper modulation to achieve low flicker noise corner frequency, high common mode rejection (CMRR) and low noise efficiency factor (NEF). The proposed circuit has been implemented in the 0.5um CMOS ON-semiconductor process and consumes 16uW of power. The post-layout simulated gain accuracy is better than 94% for gain values from 20dB to 60dB, measured NEF is 7.8 and CMRR is better than 100dB.

A 1-G?? CMOS transimpedance amplifier (TIA) suitable for processing sub-nA-level currents in electrochemical biosensor signal-acquisition circuits is presented. Use of a two-stage active transconductor provides resistive feedback in place of a large-area linear resistor. The TIA feedback loop is engineered to suppress output offset caused by DC input leakage currents of ??0.9 nA. A mechanism to tune the low-frequency cutoff of the TIA from 0.7 Hz to 500 Hz is implemented which permits operation under variable environmental conditions. Simulated and experimental results from a custom TIA fabricated in a 3.3-V 0.35-??m CMOS process are presented.

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