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Capacitive communication using human body as a electrical channel has attracted much attention in the area of personal area networks (PANs) since its introduction by Zimmerman in 1995. The reason being that the personal information and communication appliances are becoming an integral part of our daily lives. The advancement in technology is also helping a great deal in making them interesting,useful and very much affordable. If we interconnect these body-based devices with capacitive communication approach in a manner appropriate to the power, size, cost and functionality, it lessens the burden of supporting a communication channel by existing wired and wireless technologies. More than that, using body as physical communication channel for a PAN device compared to traditional radio transmission seems to have a lot of inherent advantages in terms of power and security etc. But still a lot of feasibility and reliability issues have to be addressed before it is ready for prime time. This promising technology is recently sub-classified into body area networks (BAN) and is currently under discussion in the IEEE 802.15.6 Task Group for addressing the technical requirements to unleash its full potential for BANs. This could play a part in Ericsson's envision of  50 billion connections by 2020. This thesis work is part of the main project to investigate the models, interface and derive requirements on the analog-front-end (AFE) required for the system. Also to suggest a first order model of the AFE that suits this communication system.In this thesis work the human body is modeled along with interfaces and transceiver to reflect the true condition of the system functioning. Various requirements like sensitivity, dynamic range, noise figure and signal-to-noise ratio (SNR) requirements are derived based on the system model. An AFE model based on discrete components is simulated, which was later used for proof of concept. Also a first order AFE model is developed based on the requirements derived. The AFE model is simulated under the assumed interference and noise conditions. The first order requirements for the submodules of the AFE are also derived. Future work and challenges are discussed.

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The Advanced L-band Phased Array Camera (ALPACA) is a wide-field astronomical receiver that will be housed on the Green Bank Telescope (GBT). This instrument features a fully cryogenic 69-element phased array feed (PAF) front end and digital beamformer back end. It will provide a wide and continuous field of view at L-band and high sensitivity with a system noise temperature below 27 K. Transport of the received astronomical signals on 138 individual channels from prime focus of the GBT to the digital back end -- over a distance of 3 km -- will be provided by a custom RF-over-fiber (RFoF) system. The development and experimental verification of the custom RFoF link are presented. A 16-channel fiber receiver board custom-tailored for attachment to the Xilinx ZCU216 RF system-on-chip (RFSoC) provides minimum isolation of 36 dB between channels, a gain repeatability within 3 dB between channels, and less than 2 dBpp gain ripple. Full link tests on the RFoF system, including fiber transmitter and receiver, indicate less than .89 K contribution to ALPACA's overall system noise temperature while providing 25 to 46 dB of linear dynamic range and 30 to 38 dB of spurious-free dynamic range across 1300-1720 MHz. These results meet specified design requirements and affirm that the RFoF system will allow ALPACA to achieve high sensitivity and operate as a wide-field astronomical receiver on the GBT. Measurements and models of the ALPACA cross-dipole element and low noise amplifier are also given. The dipole model is resilient to changes to cryostat structure and the measurements and models of the as-built dipole are in agreement. The cryogenic low noise amplifiers perform as expected under room temperature operation in terms of gain, noise, and linearity. These results validate that the front-end technology is on track to meet specifications and will allow ALPACA to achieve instrument objectives.

<p>Rapid development in CMOS technology has resulted in its suitability for the implementation of readout front-end systems in terms of high integration density, and low power consumption yet at the same time posing many challenges for analog circuits design like readout front-end. One of the significant challenges is the low noise design for high speed front-end systems, while at the same time minimizing the power consumption as much as possible.</p><p>A high speed, low noise, low power, and programmable readout front-end system is designed and implemented for an X-ray detector in CMOS 0.18 m technology in this thesis work. The front-end system has a peaking time of 10 ns, which is the highest speed ever reported in the published work. The front-end system is designed to achieve low noise in terms of ENC, and a low power consumption of 2.9 mW. The detector capacitance is the most dominating parameter to low noise, which in turn is directly related to the power consumption. In this thesis work an ENC of 435 electrons is achieved for a detector capacitance of 5 pF and an ENC of 320 electrons for a detector capacitance of 3 pF. Based on the comparison to related published work, a performance improvement of at least two times is achieved taking peaking time, power, ENC, and detector capacitance all into consideration. The output pulse after amplification has peak amplitude of 300 mV for a maximum injected charge of 40000 electrons from the detector.</p><p>The readout front-end system noise performance is strongly dependent on the input MOSFET type, size, and biasing. In this work a PMOS has been selected and optimized as the input device due to its smaller 1/f noise and high gain as compare to NMOS when biased at same currents. The architecture designed in this work consists of a folded cascode CSA with extra cascode in first stage, a pole-zero cancellation circuit to eliminate undershoot, a shaper amplifier, and integrators using Gm-C filter technique. All of these components are optimized for low power while meeting the noise requirements. The whole front-end system is programmed for peaking times of 10, 20, and 40 ns. The programmability is achieved by switching different capacitors and resistors values for all the poles and zeros in the front-end, and by switching parallel transconductance in the Gm-C filters. Finally fine tuning of all the capacitance, resistance, and transconductance values is done to achieve required performance.</p>

This thesis presents the design, implementation, and fabrication of an analog front-end (AFE) targeting 2x blind ADC-based receivers. The front-end consists of a combination of an anti-aliasing filter (AAF) and a 2-tap feed-forward equalizer (FFE) (AAF/FFE), the required clock generation circuitry (Ck Gen), 4 time-interleaved 4-b ADCs, and DeMUX. The contributions of this design are the AAF/FFE and the Ck Gen. The overall front-end optimizes the channel/filter characteristics for data-rates of 2-10 Gb/s. The bandwidth of the AAF is scalable with the data-rate and the analog 2-tap feed-forward equalizer (FFE) is designed without the need for noise-sensitive analog delay cells. The test-chip is implemented in 65-nm CMOS and the AAF/FFE occupies 152×86 μm2 and consumes 2.4 mW at 10 Gb/s. Measured frequency responses at data-rates of 10, 5, and 2 Gb/s confirm the scalability of the front-end bandwidth. FFE achieves 11 dB of high-frequency boost at 10 Gb/s.

This thesis presents the design, implementation, and fabrication of an analog front-end (AFE) targeting 2x blind ADC-based receivers. The front-end consists of a combination of an anti-aliasing filter (AAF) and a 2-tap feed-forward equalizer (FFE) (AAF/FFE), the required clock generation circuitry (Ck Gen), 4 time-interleaved 4-b ADCs, and DeMUX. The contributions of this design are the AAF/FFE and the Ck Gen. The overall front-end optimizes the channel/filter characteristics for data-rates of 2-10 Gb/s. The bandwidth of the AAF is scalable with the data-rate and the analog 2-tap feed-forward equalizer (FFE) is designed without the need for noise-sensitive analog delay cells. The test-chip is implemented in 65-nm CMOS and the AAF/FFE occupies 152×86 μm2 and consumes 2.4 mW at 10 Gb/s. Measured frequency responses at data-rates of 10, 5, and 2 Gb/s confirm the scalability of the front-end bandwidth. FFE achieves 11 dB of high-frequency boost at 10 Gb/s.

Rapid development in CMOS technology has resulted in its suitability for the implementation of readout front-end systems in terms of high integration density, and low power consumption yet at the same time posing many challenges for analog circuits design like readout front-end. One of the significant challenges is the low noise design for high speed front-end systems, while at the same time minimizing the power consumption as much as possible. A high speed, low noise, low power, and programmable readout front-end system is designed and implemented for an X-ray detector in CMOS 0.18 m technology in this thesis work. The front-end system has a peaking time of 10 ns, which is the highest speed ever reported in the published work. The front-end system is designed to achieve low noise in terms of ENC, and a low power consumption of 2.9 mW. The detector capacitance is the most dominating parameter to low noise, which in turn is directly related to the power consumption. In this thesis work an ENC of 435 electrons is achieved for a detector capacitance of 5 pF and an ENC of 320 electrons for a detector capacitance of 3 pF. Based on the comparison to related published work, a performance improvement of at least two times is achieved taking peaking time, power, ENC, and detector capacitance all into consideration. The output pulse after amplification has peak amplitude of 300 mV for a maximum injected charge of 40000 electrons from the detector. The readout front-end system noise performance is strongly dependent on the input MOSFET type, size, and biasing. In this work a PMOS has been selected and optimized as the input device due to its smaller 1/f noise and high gain as compare to NMOS when biased at same currents. The architecture designed in this work consists of a folded cascode CSA with extra cascode in first stage, a pole-zero cancellation circuit to eliminate undershoot, a shaper amplifier, and integrators using Gm-C filter technique. All of these components are optimized for low power while meeting the noise requirements. The whole front-end system is programmed for peaking times of 10, 20, and 40 ns. The programmability is achieved by switching different capacitors and resistors values for all the poles and zeros in the front-end, and by switching parallel transconductance in the Gm-C filters. Finally fine tuning of all the capacitance, resistance, and transconductance values is done to achieve required performance.

No description available.