Global ETD Search

1	High Speed Clock and Data Recovery Techniques Abiri, Behrooz 01 December 2011 (has links) This thesis presents two contributions in the area of high speed clock and data recovery systems. These contributions are focused on the fast phase recovery and adaptive equalization techniques. The first contribution of this thesis is an adaptive engine for a 2x blind sampling receiver. The proposed adaptation engine is able to find the phase-dependent DFE coefficients of the receiver on the fly. The second contribution is a burst-mode clock and data recovery architecture which uses an analog phase interpolator. The proposed burst-mode CDR is capable of locking to the first data transition it receives. The phase interpolator uses the inherent timing information in the data transition to rotate the phase of a reference clock and align it with the incoming data edge. The feasibility of the concept is demonstrated through fabrication and measurements. CDR Burst-Mode receiver equalization adaptation ADC-based Receiver Blind Sampling CMOS PON 0544
2	High Speed Clock and Data Recovery Techniques Abiri, Behrooz 01 December 2011 (has links) This thesis presents two contributions in the area of high speed clock and data recovery systems. These contributions are focused on the fast phase recovery and adaptive equalization techniques. The first contribution of this thesis is an adaptive engine for a 2x blind sampling receiver. The proposed adaptation engine is able to find the phase-dependent DFE coefficients of the receiver on the fly. The second contribution is a burst-mode clock and data recovery architecture which uses an analog phase interpolator. The proposed burst-mode CDR is capable of locking to the first data transition it receives. The phase interpolator uses the inherent timing information in the data transition to rotate the phase of a reference clock and align it with the incoming data edge. The feasibility of the concept is demonstrated through fabrication and measurements. CDR Burst-Mode receiver equalization adaptation ADC-based Receiver Blind Sampling CMOS PON 0544
3	A 5Gb/s Speculative DFE for 2x Blind ADC-based Receivers in 65-nm CMOS Sarvari, Siamak 16 September 2011 (has links) This thesis proposes a decision-feedback equalizer (DFE) scheme for blind ADC-based receivers to overcome the challenges introduced by blind sampling. It presents the design, simulation, and implementation of a 5Gb/s speculative DFE for a 2x blind ADC-based receiver. The complete receiver, including the ADC, the DFE, and a 2x blind clock and data recovery (CDR) circuit, is implemented in Fujitsu’s 65-nm CMOS process. Measurements of the fabricated test-chip confirm 5Gb/s data recovery with bit error rate (BER) less than 1e−12 in the presence of a test channel introducing 13.3dB of attenuation at the Nyquist frequency of 2.5GHz. The receiver tolerates 0.24UIpp of high-frequency sinusoidal jitter (SJ) in this case. Without the DFE, the BER exceeds 1e−8 even when no SJ is applied. high-speed signaling decision-feedback equalizer (DFE) blind sampling ADC-based receiver speculative look-ahead clock and data recovery (CDR) blind oversampling CMOS jitter tolerance eye diagram equalizer 0544
4	Analog Front-end Design for 2x Blind ADC-based Receivers Tahmoureszadeh, Tina 16 September 2011 (has links) This thesis presents the design, implementation, and fabrication of an analog front-end (AFE) targeting 2x blind ADC-based receivers. The front-end consists of a combination of an anti-aliasing filter (AAF) and a 2-tap feed-forward equalizer (FFE) (AAF/FFE), the required clock generation circuitry (Ck Gen), 4 time-interleaved 4-b ADCs, and DeMUX. The contributions of this design are the AAF/FFE and the Ck Gen. The overall front-end optimizes the channel/filter characteristics for data-rates of 2-10 Gb/s. The bandwidth of the AAF is scalable with the data-rate and the analog 2-tap feed-forward equalizer (FFE) is designed without the need for noise-sensitive analog delay cells. The test-chip is implemented in 65-nm CMOS and the AAF/FFE occupies 152×86 μm2 and consumes 2.4 mW at 10 Gb/s. Measured frequency responses at data-rates of 10, 5, and 2 Gb/s confirm the scalability of the front-end bandwidth. FFE achieves 11 dB of high-frequency boost at 10 Gb/s. High-speed signaling chip-to-chip communication analog front-end equalization clock and data recovery feed-forward equalization receiver ADC-based receiver blind receiver channel 0544
5	A 5Gb/s Speculative DFE for 2x Blind ADC-based Receivers in 65-nm CMOS Sarvari, Siamak 16 September 2011 (has links) This thesis proposes a decision-feedback equalizer (DFE) scheme for blind ADC-based receivers to overcome the challenges introduced by blind sampling. It presents the design, simulation, and implementation of a 5Gb/s speculative DFE for a 2x blind ADC-based receiver. The complete receiver, including the ADC, the DFE, and a 2x blind clock and data recovery (CDR) circuit, is implemented in Fujitsu’s 65-nm CMOS process. Measurements of the fabricated test-chip confirm 5Gb/s data recovery with bit error rate (BER) less than 1e−12 in the presence of a test channel introducing 13.3dB of attenuation at the Nyquist frequency of 2.5GHz. The receiver tolerates 0.24UIpp of high-frequency sinusoidal jitter (SJ) in this case. Without the DFE, the BER exceeds 1e−8 even when no SJ is applied. high-speed signaling decision-feedback equalizer (DFE) blind sampling ADC-based receiver speculative look-ahead clock and data recovery (CDR) blind oversampling CMOS jitter tolerance eye diagram equalizer 0544
6	Analog Front-end Design for 2x Blind ADC-based Receivers Tahmoureszadeh, Tina 16 September 2011 (has links) This thesis presents the design, implementation, and fabrication of an analog front-end (AFE) targeting 2x blind ADC-based receivers. The front-end consists of a combination of an anti-aliasing filter (AAF) and a 2-tap feed-forward equalizer (FFE) (AAF/FFE), the required clock generation circuitry (Ck Gen), 4 time-interleaved 4-b ADCs, and DeMUX. The contributions of this design are the AAF/FFE and the Ck Gen. The overall front-end optimizes the channel/filter characteristics for data-rates of 2-10 Gb/s. The bandwidth of the AAF is scalable with the data-rate and the analog 2-tap feed-forward equalizer (FFE) is designed without the need for noise-sensitive analog delay cells. The test-chip is implemented in 65-nm CMOS and the AAF/FFE occupies 152×86 μm2 and consumes 2.4 mW at 10 Gb/s. Measured frequency responses at data-rates of 10, 5, and 2 Gb/s confirm the scalability of the front-end bandwidth. FFE achieves 11 dB of high-frequency boost at 10 Gb/s. High-speed signaling chip-to-chip communication analog front-end equalization clock and data recovery feed-forward equalization receiver ADC-based receiver blind receiver channel 0544

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