Neural recording systems have attracted an increasing amount of attention in recent years, and researchers have put major efforts into designing and developing devices that can record and monitor neural activity. Understanding the functionality of neurons can be used to develop neuroprosthetics for restoring damages in the nervous system. An analog front-end block is one of the main components in such systems, by which the neuron signals are amplified and processed for further analysis. In this work, our goal is to design and implement a field-programmable 16-channel analog front-end block, where its programmability is used to deal with process variation in the chip. Each channel consists of a two-stage amplifier as well as a band-pass filter with digitally tunable low corner frequency. The 16 recording channels are designed using four different architectures. The first group of recording channels employs one low-noise amplifier (LNA) as the first-stage amplifier and a fully differential amplifier for the second stage along with an NMOS transistor in the feedback loop. In the second group of architectures, we use an LNA as the first stage and a single-ended amplifier for implementing the second stage. Groups three and four have the same design as groups one and two; however the NMOS transistor in the feedback loop is replaced by two PMOS transistors. In our design, the circuits are optimized for low noise and low power consumption. Simulations result in input-referred noise of 6.9 ??Vrms over 0.1 Hz to 1 GHz. Our experiments show the recording channel has a gain of 77.5 dB. The chip is fabricated in AMS 0.35 ??m CMOS technology for a total die area of 3 mm??3 mm and consumes 2.7 mW power from a 3.3 V supply. Moreover, the chip is tested on a PCB board that can be employed for in-vivo recording.

abstract: This thesis presents a gas sensor readout IC for amperometric and conductometric electrochemical sensors. The Analog Front-End (AFE) readout circuit enables tracking long term exposure to hazardous gas fumes in diesel and gasoline equipments, which may be correlated to diseases. Thus, the detection and discrimination of gases using microelectronic gas sensor system is required. This thesis describes the research, development, implementation and test of a small and portable based prototype platform for chemical gas sensors to enable a low-power and low noise gas detection system. The AFE reads out the outputs of eight conductometric sensor array and eight amperometric sensor arrays. The IC consists of a low noise potentiostat, and associated 9bit current-steering DAC for sensor stimulus, followed by the first order nested chopped £U£G ADC. The conductometric sensor uses a current driven approach for extracting conductance of the sensor depending on gas concentration. The amperometric sensor uses a potentiostat to apply constant voltage to the sensors and an I/V converter to measure current out of the sensor. The core area for the AFE is 2.65x0.95 mm2. The proposed system achieves 91 dB SNR at 1.32 mW quiescent power consumption per channel. With digital offset storage and nested chopping, the readout chain achieves 500 fÝV input referred offset. / Dissertation/Thesis / Ph.D. Electrical Engineering 2011

The Analog to Digital Converter (ADC) is an inevitable part of video AnalogFront Ends (AFE) found in the electronic displays today. The need to integratemore functionality on a single chip (there by shrinking area), poses great designchallenges in terms of achieving low power and desired accuracy.The thesis initially focuses upon selection of suitable Analog to Digital Converter(ADC) architecture for a high definition video analog front end. SuccessiveApproximation Register (SAR) ADC is the selected architecture as it scales downwith technology, has very less analog part and has minimal power consumption.In second phase a mathematical model of a Time-Interleaved Successive ApproximationRegister (TI-SAR) ADC is developed which emulates the behavior ofSAR ADC in Matlab and the errors that are characteristic of the time interleavedstructure are modeled.In the third phase a behavioral model of TI-SAR ADC having 16 channels and12 bit resolution, is built using the top-down methodology in Cadence simulationtool. All the modules were modeled at behavioral level in Verilog-A. The functionalityof the model is verified by simulation using signal of 30 MHz and clockfrequency of 300 MHz, using a supply voltage of 1.2 V. The desired SNDR (Signalto Noise Distortion ratio) 74 dB is achieved.In the final phase two architectures of comparators are implemented in 65nmtechnology at schematic level. Simulation results show that SNDR of 71 dB isachievable with a minimal power consumption of 169.6 μWper comparator runningat 300 MHz.NyckelordKeywords

Three different chip design topics associated with their respective applications are proposed in this thesis. The first topic is the implementation of an FIFO memory design for 8-to-32 data exchange bus. An FIFO memory architecture is proposed to be utilized in data exchange between processing units which possess non-homogeneous bus widths. Neither arbiter logics nor modules are required in such a design to determine input sequences or output sequences. Hence, the delay is drastically shortened. The second topic is focused on the implementation of an analog front-end of digital cordless headset baseband controller. The integrated analog and digital interface IC provides an interface for analog and digital communication. It converts an analog signal into an 8-bit digital signal, which will be processed by the baseband controller. It also converts an 8-bit digital voice data into an analog voice signal. In addition, a built-in oscillator is included in the design, which provides a global clock signal. The third topic is to carry out an DC/DC converter with a built-in voltage detector. The converter can convert 1.5V input voltage to 2.7V output voltage. A portable system can use only one single battery to power on by this circuit. It also contains a voltage detector to indicate whether the output voltage meets the pre-determined level.

A critical and important part of the medical diagnosis is the montioring of the biopotential signals. Patients are always connected to a bulky and mains-powered instrument. This not only restricts the mobility of the patients but also bring discomfort to them. Meanwhile, the measureing time can not last long thus affecting the effects of the diagnosis. Therefore, there is a high demand for low-power and small size factor ambulatory biopotential measurement systems. In addtion, the system can be configured for different biopotential applications.The ultimate goal is to implement a system that is both invisible and comfortable. The systems not onlyincrease the quality of life, but also sharply decrease the cost of healthcare delivery. In this paper, a continuously tunable gain and bandwidth analog front-end for ambulatory biopotential measurement systems is presented. The front-end circuit is capable of amplifying and conditioning different biopsignals. To optimize the power consumption and simplify the system architecture, the front-end only adopts two-stage amplifiers. In addition, careful design of the critical transistors eliminates the need of chopping circuits. The front-end is pure analog without interference from digital parts like chopping and switch capacitor circuits. The chip is fabricated under SMIC 0.18 μm CMOS process. The input-referred noise of the system is only 1.19 μVrms (0.48-2000Hz).Although the power consumption is only 32.1 μW under 3V voltage supply, test results show that the chip can successfully extract biopotential signals.

Body-channel communication (BCC) is based on the principle of electrical field data transmission attributable to capacitive coupling through the human body. It is gaining importance now a day in the scenario of human centric communication because it truly offers a natural means of interaction with the human body. Traditionally, near field communication (NFC) considers as a magnetic field coupling based on radio frequency identification (RFID) technology. The RFID technology also limits the definition of NFC and thus reduces the scope of a wide range of applications. In recent years BCC, after its first origin in 1995, regain importance with its valuable application in biomedical systems. Primarily, KAIST and Philips research groups demonstrate BCC in the context of biomedical remote patient health monitoring system. BCC transceiver mainly consists of two parts: one is digital baseband and the other is an analog front end (AFE). In this thesis, an analog front end receiver has presented to support the overall BCC. The receiver (Rx) architecture consists of cascaded preamplifier and Schmitt trigger. When the signals are coming from the human body, they are attenuated around 60 dB and gives weak signals in the range of mV. A high gain preamplifier stage needs to amplify these weak signals and make them as strong signals. The preamplifier single stage needs to cascade for the gain requirement. The single stage preamplifier, which is designed with ST65 nm technology, has an open loop gain of 24.01 dB and close loop gain of 19.43 dB. A flipped voltage follower (FVF) topology is used for designing this preamplifier to support the low supply voltage of 1 V because the topology supports low voltage, low noise and also low power consumption. The input-referred noise is 8.69 nV/sqrt(Hz) and the SNR at the input are 73.26 dB. The Schmitt trigger (comparator with hysteresis) is a bistable positive feedback circuit. It builds around two stage OTA with lead frequency compensation. The DC gain for this OTA is 26.94 dB with 1 V supply voltage. The corner analyzes and eye diagram as a performance matrix for the overall receiver are also included in this thesis work.

Modern communication systems require higher data rates which have increased thedemand for high speed transceivers. For a system to work efficiently, all blocks ofthat system should be fast. It can be seen that analog interfaces are the main bottleneckin whole system in terms of speed and power. This fact has led researchersto develop high speed analog to digital converters (ADCs) with low power consumption.Among all the ADCs, flash ADC is the best choice for faster data conversion becauseof its parallel structure. This thesis work describes the design of such a highspeed and low power flash ADC for analog front end (AFE) of a transceiver. Ahigh speed highly linear track and hold (TnH) circuit is needed in front of ADCwhich gives a stable signal at the input of ADC for accurate conversion. Twodifferent track and hold architectures are implemented, one is bootstrap TnH andother is switched source follower TnH. Simulations show that high speed with highlinearity can be achieved from bootstrap TnH circuit which is selected for the ADCdesign.Averaging technique is employed in the preamplifier array of ADC to reduce thestatic offsets of preamplifiers. The averaging technique can be made more efficientby using the smaller number of amplifiers. This can be done by using the interpolationtechnique which reduces the number of amplifiers at the input of ADC. Thereduced number of amplifiers is also advantageous for getting higher bandwidthsince the input capacitance at the first stage of preamplifier array is reduced.The flash ADC is designed and implemented in 150 nm CMOS technology for thesampling rate of 1.6 GSamples/sec. The bootstrap TnH consumes power of 27.95mW from a 1.8 V supply and achieves the signal to noise and distortion ratio(SNDR) of 37.38 dB for an input signal frequency of 195.3 MHz. The ADC withideal TnH and comparator consumes power of 78.2 mW and achieves 4.8 effectivenumber of bits (ENOB).

Body coupled communication (BCC) is a hot topic in personal networking domain. Many works arepublished suggesting different architectures for BCC since its inception in 1995 by Zimmerman. The number ofelectronic gadgets used by a single person increases as time pass by. Its a tedious job to transfer data betweenthen from a user point of view. Many of these gadgets can share their resources and save power and money.The existing wired or wireless networks does not meet the requirements for this network like scalable data rate,security etc. So here comes the novel idea of using human body as communication medium. The aim of thisthesis is to realize a hardware for BCC based on wide band signaling as part of a big project.The human body consists of 70% of water. This property makes the human body a fairly good conductor.By exploiting this basic property makes the BCC possible. A capacitance is formed if we place a metal platenear to the human body with the skin as a dielectric. This capacitance forms the interface between the humanbody and the analog front-end of the BCC transceiver. Any other metal structures near to the human body canattenuate the signal.A first-order communication link is established in software by the human body model and the transceiver inthe loop along with noise and interference. This communication link is used to verify the human body modeland the base band model done as part of the same big project. Based on the results a hardware prototype isimplemented. Measurements are taken in different scenarios using the hardware setup. The trade-off betweendesign parameters are discussed based on the results. At the end, it suggests a road map to take the projectfurther.

In this thesis, we studied the narrowband power line communication system. This system mainly utilizes the 60Hz power line as the medium to transmit network signals. In the beginning, we studied the power line channel characteristics and the coupling circuit structure, that was used to couple the signal to the power line. Impedance mismatch and signal attenuation may occur when the loading in the power line network changes. To this end we added a driver to the coupling circuit to reduce the output impedance, and hence enhance signal magnitude. In addition, we add the cross-phase coupling circuit with bandpass filter characteristics at the 220V socket. It was found that our cross-phase coupling circuit was able to improve the performance of the power line communication system when cross-phase transmission took place. Finally, we simulated the indoor power line network environment, measured several kinds of residential appliance noise and analyzed the influence on the power line communication system of the appliance noise.

RF receiver improvements in size, weight, power, and sensitivity are constant goals in the wireless communications community. The combination of phased array antenna systems with high speed analog to digital converters helps engineers meet these goals, because many of the analog components and tasks found in a traditional receive chain are moved into the digital domain. Although the hard work of signal reception is moved into digital signal processing, digital receivers rely on a high performance analog front end to properly condition a signal before analog to digital conversion. In this thesis, two RF front ends are developed for direct sampling L-band phased array receiver applications, which comprise the two main chapters of this document. Both RF front ends are developed on low cost, quick turnaround time PCB materials. Results for system gain and noise figure are presented for each front end. First, the development of an L-band analog front end for a direct sampling GPS phased array receiver is described, with particular attention to gain and noise figure in context of the full system link budget. The RF front end for the GPS phased array receiver meets design expectations by achieving a system gain of 65 dB and a system noise figure of 1.5 dB at the GPS L1 frequency. Second, the redesign and improvement of the Advanced L-band Phased Array Camera (ALPACA) RF over fiber transmitter is documented. New mechanical and electrical design requirements were brought on from the change of target observatory from the collapsed Arecibo obervatory in Puerto Rico, to the Greenbank Observatory in Greenbank, West Virginia. The ALPACA RF over fiber signal transport system with the redesigned transmitter reaches the design expectation of a system noise temperature contribution less than 1 K. Average gain of the RF over fiber system is 49 dB, gain differences between channels are less than 2 dB, and isolation between channels is better than 35 dB. Under optimal conditions, the noise figure of the RF over fiber link is 2.4 dB (213.3 K), which allows for up to 11 dB of attenuation to be added to any given transmit channel to level the gain across all 138 ALPACA channels.