Successive Approximation (SAR) analog-to-digital converters are used extensively in biomedical applications such as CAT scan due to the high resolution they offer. Capacitor mismatch in the SAR converter is a limiting factor for its accuracy and resolution. Without some form of calibration, a SAR converter can only achieve 10 bit accuracy. In industry, the CAL-DAC approach is a popular approach for calibrating the SAR ADC, but this approach requires significant test time. This thesis applies the“Split-ADC" architecture with a deterministic, digital, and background self-calibration algorithm to the SAR converter to minimize test time. In this approach, a single ADC is split into two independent halves. The two split ADCs convert the same input sample and produce two output codes. The ADC output is the average of these two output codes. The difference between these two codes is used as a calibration signal to estimate the errors of the calibration parameters in a modified Jacobi method. The estimates are used to update calibration parameters are updated in a negative feedback LMS procedure. The ADC is fully calibrated when the difference signal goes to zero on average. This thesis focuses on the specific implementation of the“Split-ADC" self-calibrating algorithm on a 16 bit, 1 MS/s differential SAR ADC. The ADC can be calibrated with 105 conversions. This represents an improvement of 3 orders of magnitude over existing statistically-based calibration algorithms. Simulation results show that the linearity of the calibrated ADC improves to within ±1 LSB.

This thesis focuses on the performace of pipeline converters and their integration on mixed signal processes. With this in mind, a 12-b 50MHz pipeline ADC has been realized in a 0.6um digital CMOS process. The architecture is based on a 1.5-b per stage structure utilizing digital correction for the first six stages. A differeintial switched capacitor circuit consisting of a cascode gm-c op-amp with 250MHz of bandwidth is used for sampling and amplification in each stage. Comparators with an internal offset voltage are used to implement the decision levels required for the 1.5-b per stage structure. Correction of the pipeline is accomplished by measuring the offset and gain of each of the first six stages using subsequent stages. The measured values are used to calculate digtal values the compensate for the inaccuracies of the analog pipeline. Corrected digital values for each stage are stored in the pipeline and used to create corrected output codes. Errors caused by measuring the first six stages using uncalibrated stages are minimized by using extra switching circuitry during calibration.

A multiple-input-multiple-output, or MIMO, receiver receives multiple data streams in the same frequency band at the same time, significantly improving spectral efficiency. It has to preserve all the antenna aperture information and use it to deliver as many data streams as the antenna count. As the number of antennas increases, implementing a MIMO receiver system in the analog domain becomes difficult. A digital MIMO receiver architecture that digitizes all the antenna inputs on the element level offers multiple advantages. Digital MIMO signal processing is flexing and powerful. Complex space-time array processing is supported and so is digital array calibration. Therefore, the digital MIMO receiver architecture has become the most promising architecture for future massive MIMO systems. However, the digital MIMO receiver architecture has a disadvantage, namely that the spatial selectivity feature is missing in the RF/analog domain. At the target frequency band, multiple spatial signals can arrive at the antenna array at different power levels. Conventional spectral filtering is ineffective at in-band frequency so all the spatial signals have to co-exist in all the receiver elements and the following analog-to-digital converters (A/Ds). The instantaneous dynamic range required for these RF/analog and mixed-signal circuits will be limited by the strongest spatial signal on the upper bound, and the weakest spatial signal on the lower bound. A high instantaneous dynamic range requirement directly translates to high power consumption and high cost. Therefore, the recovery of spatial selectivity in the RF/analog domain is necessary. The first thrust toward recovering RF/analog spatial selectivity in a digital MIMO receiver is the scalable spatial notch suppression technique. Knowing the direction of a strong spatial blocker, a spatial notch, instead of beams, can be synthesized to the blocker direction to filter it out. This means that all the analog baseband outputs will show high conversion gains to signals from all directions but one, namely the blocker direction. In this way, high sensitivity is preserved in most directions to receiver multiple weak spatial signals simultaneously, which will be digitized, and separated in the digital domain. In the blocker direction, a low conversion gain filters the blocker out, preventing it from demanding high dynamic range for all of the RF/analog circuits and the A/Ds. In order to synthesize the scalable spatial notch, a spatial notch filter (SNF) is designed to provide lower input impedance in the blocker direction and high impedance in other directions. Using this spatially modulated impedance to load a current mode receiver leads to spatially modulated conversion gain. A transparent RF front-end translates this impedance to the antenna interface to achieve spatial notch suppression right at the antennas. A feedforward spatial notch canceler (FF SNC) uses the available isolated blocker information to improve spatial suppression ratio. The spatial notch suppression is scalable through a baseband node, allowing the tiling of multiple ICs on the same PCB for larger scale MIMO systems. A prototype receiver array was implemented with a 65nm CMOS process. Experimental results showed 32dB steerable spatial notch suppression, more than 19db of suppression inside the notch direction across all frequencies. In-band output-referred IP3 was improved from -10dBV to +24dBV, from outside to inside the notch direction, and IIP3 was also improved from +11dBm to +18dBm. Single-element equivalent double-sideband noise figure (NFDSB,eq) was 2.2 to 4.6dB across the 0.1 to 1.7GHz operating frequency range, also showing an improvement compared to other multi-antenna receivers at similar frequency ranges. A second thrust is an RF/analog arbitrary spatial filtering receiver. Instead of filtering out strong spatial blockers, a more general and robust way to recover spatial selectivity is to impose an arbitrary spatial response that adaptively equalizes the power levels of all the spatial signals. In this way, all the spatial signals should have the same power level when reaching the A/Ds, allowing the use of low-power A/Ds with low dynamic ranges, which are essential for the realization of the digital massive MIMO solution. Such an arbitrary spatial filtering response requires the ability to synthesize multiple spatial notches that can be independently steered, the depth of the notches free adjusted. In addition, a few performance metrics need to be improved based on the first work. Spatial suppression ratio was limited by the lack of magnitude control in the first work. In-band in-notch linearity performance was limited by the use of voltage mode gyrators that requires a band-limiting high-impedance node, which also limits spatial suppression bandwidth. Also, the antenna array dimensions scale inversely with operating frequency. So pushing the receiver array to work at higher frequency is also desired. Toward these goals, a 65nm CMOS prototype receiver array was implemented. Wideband current-mode receiver front-ends that consist of inverter-based LNTAs and passive mixers can work up to 3.1GHz. A baseband current-mode beamformer can synthesize virtual grounds at the output nodes in the target notch directions, providing not only an arbitrary spatial response but also an baseband input impedance that is also spatially modulated, allowing spatial filtering at the LNTA output nodes. Current mode operation avoids the use of band-limiting high impedance nodes for strong spatial signals, leading to superior linearity and wideband spatial suppression. This 4-element prototype measured more than 50dB of spatial suppression ratios with single-notch settings across all measured directions. Up to three notches can be synthesized, each of which can be independently steered and its depth freely adjusted. An in-band OIP3 of +34dBV was measured, 10dB higher than the first work, due to the current mode operation. A 20dB suppression bandwidth of 320MHz, or equivalently 64% was measured, more than 20× improvement than the first work, also due to the current mode operation. On a separate note, an ultra-wideband LNTA was also designed for an RF channelizing receiver work. This two-stage LNTA makes use of a gm-boosted current mirror structure to harness the linearity advantage of a current mirror, the low-noise input matching of the feedback structure, the high transconductance gain of a two-stage structure and an ultra-wideband input matching advantage of a gyrator. The implemented 65nm CMOS prototype is fully integrated, and provides 242mS peak transconductance gain over 0.6-9.6GHz operating frequency range. It achieves 4.5dB of NF and +6.5dBm of IIP3. In summary, RF/analog spatial selectivity can be recovered in innovative methods to relax the dynamic range requirement for all the RF/analog circuits together with the following A/Ds in a digital MIMO receiver. The scalable spatial notch suppression technique and the arbitrary spatial filtering technique allow the use of low-power A/Ds, which are essential for truly massive MIMO systems with manageable power consumption.

Chi-Hong, Chan. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2004. / Includes bibliographical references (leaves 114-117). / Abstracts in English and Chinese. / Abstract --- p.i / 摘要 --- p.iii / Acknowledgements --- p.iv / Table of Contents --- p.vi / List of Figures --- p.x / List of Tables --- p.xiii / Chapter 1. --- Introduction --- p.1 / Chapter 1.1. --- System on a Chip (SoC) Design Challenges --- p.1 / Chapter 1.2. --- Research Objective --- p.3 / Chapter 1.3. --- Thesis Organization --- p.3 / Chapter 2. --- Fundamentals of CMOS Current Mode A/D converters --- p.5 / Chapter 2.1. --- Overview --- p.5 / Chapter 2.2. --- Current Mode Signal Processing --- p.5 / Chapter 2.2.1. --- Voltage Mode Circuit Design Technique --- p.5 / Chapter 2.2.2. --- Current Mode Circuit Design Technique --- p.6 / Chapter 2.2.3. --- First Generation (FG) SI Memory Cell vs. Second Generation (SG) SI Memory Cell --- p.7 / Chapter 2.3. --- Ideal Nyquist Rate A/D converters --- p.9 / Chapter 2.4. --- Static Performance Parameters --- p.13 / Chapter 2.4.1. --- Differential Non-Linearity (DNL) --- p.13 / Chapter 2.4.2. --- Integral Non-Linearity (INL) --- p.13 / Chapter 2.5. --- Performance Parameters in Frequency Domain --- p.15 / Chapter 2.5.1. --- Signal-to-Noise and Distortion Ratio (SNDR) --- p.16 / Chapter 2.5.2. --- Effective Number of Bits (ENOB) --- p.16 / Chapter 2.5.3. --- Spurious Free Dynamic Range (SFDR) --- p.16 / Chapter 3. --- Proposed Current Mirror Memory Cell (CMMC) --- p.18 / Chapter 3.1. --- Overview --- p.18 / Chapter 3.2. --- Working Principle of CMMC --- p.18 / Chapter 3.3. --- CMMC vs. FG SI Cells --- p.20 / Chapter 3.4. --- Analog Delay Cell Implementation using the two kinds of memory cells --- p.21 / Chapter 3.4.1. --- Delay Cell Implementation by FG Memory Cells --- p.22 / Chapter 3.4.2. --- Delay Cell Implementation by CMMC --- p.23 / Chapter 3.4.3. --- Simulation Results --- p.24 / Chapter 3.5. --- Conclusion --- p.27 / Chapter 4. --- Architectural Design of the 12-Bit CMOS A/D Converter --- p.28 / Chapter 4.1. --- Overview --- p.28 / Chapter 4.2. --- The Floating Analog-to-Digital Converter --- p.28 / Chapter 4.3. --- Conversion Algorithm --- p.32 / Chapter 4.4. --- Accuracy Considerations Due to Circuit Non-Idealities --- p.34 / Chapter 4.4.1. --- Gain Error of Residual Generator --- p.34 / Chapter 4.4.2. --- Offset Error of Residual Generator --- p.36 / Chapter 4.5. --- Speed Consideration --- p.36 / Chapter 4.6. --- Power Consumption vs. No. of Bits per Stage --- p.38 / Chapter 4.7. --- Final Architectural Design --- p.40 / Chapter 5. --- A/D Converter Implementation using CMMC --- p.41 / Chapter 5.1. --- Overview --- p.41 / Chapter 5.2. --- Current Sample-and-Hold --- p.41 / Chapter 5.2.1. --- Signal Independent CFT Cancellation --- p.43 / Chapter 5.2.2. --- Signal Dependent CFT Cancellation --- p.44 / Chapter 5.2.3. --- Complete CFT Cancellation --- p.45 / Chapter 5.2.4. --- CFT Cancellation by Transmission Gate --- p.45 / Chapter 5.2.5. --- CFT Cancellation by Dummy Switches --- p.47 / Chapter 5.3. --- Common Mode Feed Forward (CMFF) --- p.48 / Chapter 5.4. --- Differential Current Comparator --- p.52 / Chapter 5.4.1. --- Regenerative Latch --- p.53 / Chapter 5.4.2. --- Pre-amplifier --- p.54 / Chapter 5.5. --- Residual Generator --- p.55 / Chapter 5.6. --- Thermometer to Binary code Decoder --- p.57 / Chapter 6. --- Layout Considerations --- p.59 / Chapter 6.1. --- Overview --- p.59 / Chapter 6.2. --- Process Introduction --- p.59 / Chapter 6.3. --- Common Centroid Layout --- p.60 / Chapter 6.4. --- The Design of Power Supply Rails --- p.63 / Chapter 6.5. --- Shielding --- p.64 / Chapter 6.6. --- Layout of the whole design --- p.65 / Chapter 7. --- Simulation Results --- p.67 / Chapter 7.1. --- Overview --- p.67 / Chapter 7.2. --- Simulation Results of the Current Sample-and-Hold --- p.67 / Chapter 7.3. --- Simulation Results of the Differential Current Comparator --- p.70 / Chapter 7.4. --- Simulation Results of the overall ADC using One-Stage Simulation Result --- p.71 / Chapter 7.5. --- Power Simulation of the Overall 12-Bit ADC --- p.75 / Chapter 7.6. --- Summary --- p.78 / Chapter 8. --- Measurement Results --- p.79 / Chapter 8.1. --- Overview --- p.79 / Chapter 8.2. --- PCB Design Consideration --- p.79 / Chapter 8.3. --- Measurement Setup --- p.82 / Chapter 8.4. --- Measurement Result --- p.84 / Chapter 8.4.1. --- Static Parameters --- p.84 / Chapter 8.4.2. --- Frequency Domain Measures --- p.85 / Chapter 8.5. --- Discussion --- p.90 / Chapter 9. --- Conclusion --- p.95 / Chapter 9.1. --- Research Methodology of this Project --- p.95 / Chapter 9.2. --- Comparison between Voltage Mode and Current Mode Circuit --- p.97 / Chapter 9.3. --- Contribution of this Project --- p.98 / Chapter A. --- Appendices --- p.99 / Chapter A.I. --- Small Signal Analysis on CMMC and FG Memory Cell --- p.99 / Chapter A.II. --- The ESD Protection on the ADC --- p.102 / Chapter A.III. --- The Histogram Test to determine the DNL and INL of ADC --- p.104 / Chapter A.IV. --- Measurement Result of a Commercially Available ADC AD7820 --- p.106 / Chapter A.V. --- Pin Assignment of the Current Mode ADC --- p.109 / Chapter A.VI. --- Schematics of the Current Mode ADC --- p.111 / Chapter A.VII. --- The Chip Micrograph --- p.113 / Bibliography --- p.114

by Cheng Wang-tung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2004. / Includes bibliographical references (leaves 97-99). / Abstracts in English and Chinese. / Abstract --- p.i / 摘要 --- p.i / Acknowledgements --- p.ii / Table of Contents --- p.iii / List of Figures --- p.vii / List of Tables --- p.xi / Chapter Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivations --- p.1 / Chapter 1.2 --- Objective --- p.4 / Chapter 1.3 --- Outline --- p.4 / Chapter Chapter 2 --- Quadrature ΣΔ Modulator for A/D Conversion --- p.5 / Chapter 2.1 --- Introduction --- p.5 / Chapter 2.2 --- Oversampling ΣΔ Converter --- p.6 / Chapter 2.3 --- Theory of ΣΔ modulation --- p.6 / Chapter 2.3.1 --- Quantization noise --- p.7 / Chapter 2.3.2 --- Oversampling --- p.8 / Chapter 2.3.3 --- Noise Shaping --- p.9 / Chapter 2.3.4 --- Performance Parameter --- p.11 / Chapter 2.3.5 --- Circuit Design of ΣΔ modulator --- p.11 / Chapter 2.3.6 --- Case Study --- p.12 / Chapter 2.3.6.1 --- Transfer Function --- p.12 / Chapter 2.3.6.2 --- Noise Analysis of First Order ΣΔ Modulator --- p.13 / Chapter 2.3.6.3 --- Circuit Level Implementation: --- p.14 / Chapter 2.4 --- Choice of Architecture: Lowpass or Bandpass? --- p.15 / Chapter 2.5 --- I/Q Modulation and Image Rejection --- p.18 / Chapter 2.5.1 --- Quadrature signal --- p.18 / Chapter 2.5.2 --- I/Q Modulation --- p.19 / Chapter 2.6 --- Image Rejection in SC ΣΔ Complex Topology --- p.21 / Chapter 2.6.1 --- High Level Simulation --- p.23 / Chapter 2.6.2 --- Discussion --- p.26 / Chapter 2.7 --- Summary --- p.27 / Chapter Chapter 3 --- Capacitor Sharing Architecture --- p.28 / Chapter 3.1 --- Introduction --- p.28 / Chapter 3.2 --- Proposed mismatch free SC complex ΣΔ Modulator --- p.28 / Chapter 3.2.1 --- Principle of Operation --- p.30 / Chapter 3.3 --- Justification of the Proposed Idea --- p.35 / Chapter 3.4 --- Summary --- p.37 / Chapter Chapter 4 --- Transistor Level Circuit Design --- p.39 / Chapter 4.1 --- Introduction --- p.39 / Chapter 4.2 --- Design of ΣΔ Modulator --- p.39 / Chapter 4.2.1 --- Specification of ΣΔ Modulator --- p.40 / Chapter 4.3 --- Design of Operational Amplifier --- p.45 / Chapter 4.3.1 --- Folded-cascode Operational Amplifier --- p.45 / Chapter 4.3.2 --- Common Mode feedback --- p.47 / Chapter 4.3.3 --- Bias Circuit --- p.49 / Chapter 4.3.4 --- Simulation Results --- p.50 / Chapter 4.4 --- Design of Comparator --- p.54 / Chapter 4.4.1 --- Regenerative Feedback Comparator --- p.54 / Chapter 4.4.2 --- Simulation Results --- p.55 / Chapter 4.5 --- Design of Clock Generator --- p.56 / Chapter 4.5.1 --- Non-Overlapping clock generation --- p.57 / Chapter 4.5.2 --- Simulation Results --- p.58 / Chapter 4.6 --- Simulation Results of ΣΔ Modulator --- p.59 / Chapter 4.7 --- Simulation Results --- p.61 / Chapter 4.7.1 --- Proposed Architecture --- p.62 / Chapter 4.7.2 --- Traditional Architecture --- p.62 / Chapter 4.8 --- Summary --- p.63 / Chapter Chapter 5 --- Layout Considerations and Post-Layout Simulation --- p.65 / Chapter 5.1 --- Introduction --- p.65 / Chapter 5.2 --- Common-Centroid Structure --- p.65 / Chapter 5.3 --- Shielding Technique --- p.67 / Chapter 5.3.1 --- Shielding of device by substrate --- p.67 / Chapter 5.3.2 --- Floor Planning --- p.68 / Chapter 5.4 --- Layout of Power Rail --- p.69 / Chapter 5.5 --- Layout and Post-Layout Simulation of OpAmp --- p.70 / Chapter 5.6 --- Layout and Post-Layout Simulation --- p.74 / Chapter 5.6.1 --- Proposed Architecture --- p.75 / Chapter 5.6.2 --- Traditional Architecture --- p.77 / Chapter 5.7 --- Summary --- p.79 / Chapter Chapter 6 --- Measurement Results --- p.81 / Chapter 6.1 --- Introduction --- p.81 / Chapter 6.2 --- Considerations of PCB Design --- p.82 / Chapter 6.3 --- Measurement Setup --- p.83 / Chapter 6.4 --- Measurement Results --- p.85 / Chapter 6.4.1 --- Measurement Results of Proposed Architecture --- p.85 / Chapter 6.5 --- Summary --- p.92 / Chapter Chapter 7 --- Conclusion --- p.95 / Chapter 7.1 --- Conclusion --- p.95 / Chapter 7.2 --- Future Works --- p.96 / References --- p.97 / Appendix --- p.100 / Chapter A.1 --- Publications --- p.100 / Chapter A.2 --- Schematic of proposed front end --- p.101 / Chapter A.3 --- Schematic of SC ΣΔ modulator --- p.102 / Chapter A.4 --- Schematic of the folded-cascode amplifier --- p.103 / Chapter A.5 --- Schematic of biasing circuit --- p.104 / Chapter A.6 --- Schematic of preamplifier in comparator --- p.105 / Chapter A.7 --- Schematic of latched part in comparator --- p.106 / Chapter A.8 --- Schematic of the clock generator --- p.107

Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003. / Includes bibliographical references (p. 85-86). / The folding and interpolating technique has been introduced to CMOS analog-to- digital converter (ADC) in the 1980's. It has successfully reduced the number of comparators required while preserving the benefits of a flash ADC. However, similar to flash ADC, folding and interpolating ADC is also limited to low resolution, due to its complication in the folding operation. Cascaded folding and interpolating architecture is then adopted to alleviate the problem. The design of a 10-bit, 55MSPS ADC is presented to illustrate the merits of the architecture. Data conversion is conducted in two parallel blocks, the MSB and LSB sections. The MSB section is responsible for computing the four MSBs while the LSB section computes the remaining six LSBs. The folding and interpolation preprocessing, completed in three cascaded stages, is employed in the LSB section. The circuit functions are designed in 0.35[mu]m CMOS process with a 3.3V supply. The analog circuitry dissipates 54m W while achieving < 1 /2 LSB DNL performance in simulation. / by Yanlok Charlotte Lau. / M.Eng.

Nowadays, Multi-GHz analog-to-digital converters (ADCs) are becoming more and more popular in radar systems, software-defined radio (SDR) and wideband communications, because they can realize much higher operation speed through using many interleaved sub-ADCs to relax ADC sampling rates. Although the time interleaved ADC has some issues such as gain mismatch, offset mismatch and timing skew between each ADC channel, these deterministic errors can be solved by previous works such as digital calibration technique. However, time-interleaved ADCs require a precise sample clock to achieve an acceptable effective-numberof-bits (ENOB) which can be degraded by jitter in the sample clock. The clock generation circuits presented in this work achieves sub-picosecond jitter performance in 180nm CMOS which is suitable for time-interleaved ADC. Two different test chips were fabricated in 180nm CMOS to investigate the low jitter design technique. The low jitter delay line in two chips were designed in two different ways, but both of them utilized the low jitter design technique. In first test chip, the measured RMS jitter is 0.1061ps for each delay stage. The second chip uses the proposed low jitter Delay-Locked Loop can work from 80MHz to 120MHz, which means it can provide the time interleaved ADC with 2.4GHz to 3.6GHz low jitter sample clock, the measured delay stage jitter performance in second test chip is 0.1085ps.

This thesis presents a novel algorithmic A/D converter to be used in a biosensor. The converter is capable of a conversion rate of 1.5 bits/phase and hence the required conversion time is reduced. The proposed architecture is analyzed for non-ideal effects and compared with existing algorithmic A/D architectures. The converter needs only one op-amp, 4 comparators and 3 capacitors. Power reduction techniques are discussed with respect to the biosensor and the ADC. The ADC is designed for fabrication in a CMOS 0.18μm process. / Graduation date: 2004

Pipelined analog to digital converters (ADCs) are very important building blocks in many electronic systems such as high quality video systems, high performance digital communication systems and high speed data acquisition systems. The rapid development of these applications is driving the design of pipeline ADCs towards higher speed, higher dynamic range, lower power consumption and lower power supply voltage with the CMOS technology scaling. This trend poses great challenges to conventional pipelined ADC designs which rely on high-gain operational amplifiers (opamps) and well matched capacitors to achieve high accuracy. In this thesis, two novel accuracy improvement techniques to overcome the accuracy limit set by analog building blocks (opamps and capacitors) in the context of low-voltage and high-speed pipelined ADC design are presented. One is the time-shifted correlated double sampling (CDS) technique which addresses the finite opamp gain effect and the other is the radix-based background digital calibration technique which can take care of both finite opamp gain and capacitor mismatch. These methods are simple, easy to implement and power efficient. The effectiveness of the proposed techniques is demonstrated in simulation as well as in experiment. Two prototype ADCs have been designed and fabricated in 0.18μm CMOS technology as the experimental verification of the proposed techniques. The first ADC is a 1.8V 10-bit pipeline ADC which incorporated the time-shifted CDS technique to boost the effective gain of the amplifiers. Much better gain-bandwidth tradeoff in amplifier design is achieved with this gain boosting. Measurement results show total power consumption of 67mW at 1.8V when operating at 100MSPS. The SNR, SNDR and SFDR are 55dB, 54dB and 65dB respectively given a 1MHz input signal. The second one is a 0.9V 12-bit two-stage cyclic ADC which employed a novel correlation-based background calibration to enhance the linearity. The linearity limit set by the capacitor mismatches, finite opamp gain effects is exceeded. After calibration, the SFDR is improved by about 33dB and exceeds 80dB. The power consumption is 12mW from 0.9V supply when operating at 2MSPS. / Graduation date: 2004

This thesis proposes a novel fully digital technique for the estimation and correction of the DAC error in multi-bit delta sigma ADCs. The structure of the DAC error is indicated through a simple model for unit-element based DACs. The impact of the DAC error on the performance of ADC is then analyzed. Various techniques dealing with the DAC error are described and their drawbacks are pointed out. Based on the nature of the DAC error and the surrounding signals, a fully digital method to estimate the error from the ADC output and remove it is proposed. Simulation results are shown to support the effectiveness of the method. Simulations also show that the proposed technique can work together with the technique of adaptive compensation for quantization noise leakage in cascaded delta sigma (MASH) ADC cases. These two techniques are the foundation for the design of high speed, high resolution delta sigma ADCs with relaxed requirements on the analog circuits. To verify the proposed technique, an experimental MASH ADC was built, including the design and fabrication of a chip of a second-order multi-bit delta sigma ADC in a 1.6��m CMOS technology. The measured results show that the proposed DAC correction technique is highly effective. / Graduation date: 2004