Thesis (M.App.Sc.) - Carleton University, 2005. / Includes bibliographical references (p. 146-148). Also available in electronic format on the Internet.

Thesis (M.App.Sc.) - Carleton University, 2005. / Includes bibliographical references (p. 130-137). Also available in electronic format on the Internet.

Thesis (M.Eng.). / Written for the Dept. of Electrical and Computer Engineering. Title from title page of PDF (viewed 2009/06/17). Includes bibliographical references.

Thesis (M.App.Sc.) - Carleton University, 2007. / Includes bibliographical references (p. 168-170). Also available in electronic format on the Internet.

Thesis (Ph. D.)--Carleton University, 2001. / Includes bibliographical references (p. 296-303). Also available in electronic format on the Internet.

Thesis (M.Phil.)--Hong Kong University of Science and Technology, 2007. / Includes bibliographical references (leaves 92-95). Also available in electronic version.

Thesis (Ph. D.)--Oregon State University, 2008. / Printout. Includes bibliographical references (leaves 79-82). Also available on the World Wide Web.

In this work, we investigate circuit techniques to reduce the power consumption of Successive Approximation Register Analog-to-Digital Converter (SAR-ADC). We developed four low-power SAR-ADC design techniques, which are: 1) Low-power SAR-ADC design with split voltage reference, 2) Charge recycling techniques for low-power SAR-ADC design, 3) Low-power SAR-ADC design using two-capacitor arrays, 4) Power reduction techniques by dynamically minimizing SAR-ADC conversion cycles. Matlab simulations are performed to investigate the power saving by the proposed techniques. Simulation results show that significant power reduction can be achieved by using the developed techniques. In addition, design issues such as area overhead, design complexity associated with the proposed low-power techniques are also discussed in the thesis.

abstract: Time-interleaved analog to digital converters (ADCs) have become critical components in high-speed communication systems. Consumers demands for smaller size, more bandwidth and more features from their communication systems have driven the market to use modern complementary metal-oxide-semiconductor (CMOS) technologies with shorter channel-length transistors and hence a more compact design. Downscaling the supply voltage which is required in submicron technologies benefits digital circuits in terms of power and area. Designing accurate analog circuits, however becomes more challenging due to the less headroom. One way to overcome this problem is to use calibration to compensate for the loss of accuracy in analog circuits. Time-interleaving increases the effective data conversion rate in ADCs while keeping the circuit requirements the same. However, this technique needs special considerations as other design issues associated with using parallel identical channels emerge. The first and the most important is the practical issue of timing mismatch between channels, also called sample-time error, which can directly affect the performance of the ADC. Many techniques have been developed to tackle this issue both in analog and digital domains. Most of these techniques have high complexities especially when the number of channels exceeds 2 and some of them are only valid when input signal is a single tone sinusoidal which limits the application. This dissertation proposes a sample-time error calibration technique which bests the previous techniques in terms of simplicity, and also could be used with arbitrary input signals. A 12-bit 650 MSPS pipeline ADC with 1.5 GHz analog bandwidth for digital beam forming systems is designed in IBM 8HP BiCMOS 130 nm technology. A front-end sample-and-hold amplifier (SHA) was also designed to compare with an SHA-less design in terms of performance, power and area. Simulation results show that the proposed technique is able to improve the SNDR by 20 dB for a mismatch of 50% of the sampling period and up to 29 dB at 37% of the Nyquist frequency. The designed ADC consumes 122 mW in each channel and the clock generation circuit consumes 142 mW. The ADC achieves 68.4 dB SNDR for an input of 61 MHz. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2017

Thesis (Masters Diploma (Electrical Engineering)--Cape Technikon, Cape Town,1994 / This thesis describes the design, development and implementation of a digitising workstation for the electronics laboratory that utilises the personal computer.