This thesis presents two hybrid luminescence-based biochemical photosensory microsystems: a CMOS/microfluidic chemiluminescence contact imager, and a CMOS/thin-film fluorescence contact imager. A compact, low-power analog-to-digital converter (ADC) architecture for use in such sensory microsystems is also proposed. Both microsystems are prototyped in a standard 0.35um CMOS technology. The CMOS/microfluidic microsystem integrates a 64x128-pixel CMOS imager and a soft polymer microfluidic network. Circuit techniques are employed to reduce the dark current and circuit noise for low-level light sensitivity. Experimental validation is performed by detecting luminol chemiluminescence and electrochemiluminescence. The CMOS/thin-film microsystem integrates an existing 128x128-pixel CMOS imager and a prefabricated, high-performance optical filter. Experimental validation is performed by detecting human DNA labeled with Cyanine-3 fluorescent dye. The proposed ADC architecture employs a novel digital-to-analog converter with a flexible trade-off between the integration area and the conversion speed. The area savings and good linearity of the DAC are verified by simulations.

In an industrial and consumer electronic marketplace that is increasingly demanding greater real-world interactivity in portable and distributed devices, analog to digital converter efficiency and performance is being carefully examined. The successive approximation (SAR) analog to digital converter (ADC) architecture has become popular for its high efficiency at mid-speed and resolution requirements. This is due to the one core single bit quantizer, lack of residue amplification, and large digital domain processing allowing for easy process scaling. This work examines the traditional binary capacitive SAR ADC time and statistical information and proposes new structures that optimize ADC performance. The Ternary SAR (TSAR) uses the quantizer delay information to enhance accuracy, speed and power consumption of the overall SAR while providing multi-level redundancy. The early reset merged capacitor switching SAR (EMCS) identifies lost information in the SAR subtraction and optimizes a full binary quanitzer structure for a Ternary MCS DAC. Residue Shaping is demonstrated in SAR and pipeline configurations to allow for an extra bit of signal to noise quantization ratio (SQNR) due to multi-level redundancy. The feedback initialized ternary SAR (FITSAR) is proposed which splits a TSAR into separate binary and ternary sub-ADC structures for speed and power benefits with an inter-stage encoding that not only maintains residue shaping across the binary SAR, but allows for nearly optimally minimal energy consumption for capacitive ternary DACs. Finally, the ternary SAR ideas are applied to R2R DACs to reduce power consumption. These ideas are tested both in simulation and with prototype results. / Graduation date: 2013 / Access restricted to the OSU Community at author's request from Jan. 7, 2013 - Jan. 7, 2014

Time-interleaved analog-to-digital converters make use of parallelization to increase the rate at which an analog signal can be digitized. Using M channels at their maximum sampling frequency allows for an overall sampling frequency of M times the individual converters' sampling rate. However, the performance of interleaved systems suffers from mismatches between the sub-converters. Offset mismatches, gain mismatches, and timing mismatches all contribute to the degradation of the resolution of the ADC system. Offset and gain mismatches can be corrected for in the digital domain with minimal extra processing. However, the effects of timing mismatches (specifically, the magnitude of the spurious tones that are introduced) are dependent on the frequency of the input, so digital correction is not a trivial task. This makes a circuit-based correction mechanism a much more desirable solution to the problem. This work explores the effect of timing mismatches on interleaved analog-to-digital converter performance. A set of requirements is derived to specify the performance of a variable-delay circuit for the tuning of sample clocks. Since the mismatches can be composed of both fixed and random components, several candidate architectures are modeled for their delay and jitter performance. One candidate is selected for design, based on its jitter performance and on practical considerations. A practical implementation of the clock-adjustment circuit is designed, featuring low-noise differential clock paths with high precision delay adjustment. A means of testing the circuit and verifying the precision of adjustment is presented. The design is implemented for fabrication, and post-layout simulations are shown to demonstrate the feasibility and functionality of the design.

This dissertation presents a comprehensive design and analysis framework for system-on-a-chip analog-to-digital conversion design. The design encompasses a broad class of systems, which take advantage of system-on-a-chip complexity. This class is exemplified by an interferometric photodetector array based bio-optoelectronic sensor that is built and tested as part of the reported work. While there have been many discussions of the technical details of individual analog-to-digital converter (ADC) schemes in the literature, the importance of the analog front-end as a pre-processor for a data converter and the generalized analysis including converter encoding and decoding functions have not previously been investigated thoroughly, and these are key elements in the choice of converter designs for low-noise systems such as bio-optoelectronic sensors. Frequency domain analog front-end models of ADCs are developed to enable the architectural modeling of ADCs. The proposed models can be used for ADC statistically worst-case performance estimation, with stationary random process assumptions on input signals. These models prove able to reveal the architectural advantages of a specific analog-to-digital converter schemes quantitatively, allowing meaningful comparisons between converter designs. The modeling of analog-to-digital converters as communication channels and the ADC functional analysis as encoders and decoders are developed. This work shows that analog-to-digital converters can be categorized as either a decoder-centered design or an encoder-centered design. This perspective helps to show the advantages of nonlinear decoding schemes for oversampling noise-shaping data converters, and a new nonlinear decoding algorithm is suggested to explore the optimum solution of the decoding problem. A case study of decoder-centered and encoder-centered data converter designs is presented by applying the proposed theoretical framework. The robustness and flexibility of the resulting analog-to-digital converters are demonstrated and compared. The electrical and optical sensitivity measurements of a fabricated oversampling noise shaping analog-to-digital converter circuit are provided, and a sensor system-on-a-chip using these ADCs with integrated interferometric waveguides for bio-optoelectronic sensing is demonstrated.

Hard disk drive applications require a high Spurious Free Dynamic Range (SFDR), 6-bit Analog-to-Digital Converter (ADC) at conversion rates of 1GHz and beyond. This work proposes a robust, fault-tolerant scheme to achieve high SFDR in an av- eraging flash A/D converter using comparator chopping. Chopping of comparators in a flash A/D converter was never previously implemented due to lack of feasibility in implementing multiple, uncorrelated, high speed random number generators. This work proposes a novel array of uncorrelated truly binary random number generators working at 1GHz to chop all comparators. Chopping randomizes the residual offset left after averaging, further pushing the dynamic range of the converter. This enables higher accuracy and lower bit-error rate for high speed disk-drive read channels. Power consumption and area are reduced because of the relaxed design requirements for the same linearity. The technique has been verified in Matlab simulations for a 6-bit 1Gsamples/s flash ADC under case of process gradients with non-zero mean offsets as high as 60mV and potentially serious spot offset errors as high as 1V for a 2V peak to peak input signal. The proposed technique exhibits an improvement of over 15dB compared to pure averaging flash converters for all cases. The circuit-level simulation results, for a 1V peak to peak input signal, demon- strate superior performance. The reported ADC was fabricated in TSMC 0.18 ??mCMOS process. It occupies 8.79mm2 and consumes about 400mW from 1.8V power supply at 1GHz. The targeted SFDR performance for the fabricated chip is at least 45dB for a 256MHz input sine wave, sampled at 1GHz, about 10dB improvement on the 6-bit flash ADCs in the literature.

Thesis (Ph. D.)--Brigham Young University. Dept. of Electrical and Computer Engineering, 2004. / Includes bibliographical references (p. 153-158).

published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

Time-interleaved analog-to-digital converters make use of parallelization to increase the rate at which an analog signal can be digitized. Using M channels at their maximum sampling frequency allows for an overall sampling frequency of M times the individual converters' sampling rate. However, the performance of interleaved systems suffers from mismatches between the sub-converters. Offset mismatches, gain mismatches, and timing mismatches all contribute to the degradation of the resolution of the ADC system. Offset and gain mismatches can be corrected for in the digital domain with minimal extra processing. However, the effects of timing mismatches (specifically, the magnitude of the spurious tones that are introduced) are dependent on the frequency of the input, so digital correction is not a trivial task. This makes a circuit-based correction mechanism a much more desirable solution to the problem. This work explores the effect of timing mismatches on interleaved analog-to-digital converter performance. A set of requirements is derived to specify the performance of a variable-delay circuit for the tuning of sample clocks. Since the mismatches can be composed of both fixed and random components, several candidate architectures are modeled for their delay and jitter performance. One candidate is selected for design, based on its jitter performance and on practical considerations. A practical implementation of the clock-adjustment circuit is designed, featuring low-noise differential clock paths with high precision delay adjustment. A means of testing the circuit and verifying the precision of adjustment is presented. The design is implemented for fabrication, and post-layout simulations are shown to demonstrate the feasibility and functionality of the design.

No description available.

Analog-to-digital converters (ADCs) are required in almost all signal processing and communication systems. They are often the most critical components, since they tend to determine the overall system performance. Hence, it is important to determine their performance limitations and develop improved realizations. One of the most challenging tasks for realizing software defined radio (SDR) is to move ND conversion as close to the antenna as possible, this implies that the ADC has to sample the incoming signal with a very high sample rate (over 100 MSample/s) and with a very high resolution (14 -to -16 bits). To design and implement AID converters with such high performance, it is necessary to investigate new designing techniques. The focus in this work is on a particular type of potentially high-performance (high-resolution and highspeed) analog-to-digital conversion technique, utilizing filter banks, where two or more ADCs are used in the converter array in parallel together with asymmetric filter banks. The hybrid filter bank analog-todigital converter (HFB ADC) utilizes analog filters (analysis filters) to allocate a frequency band to each ADC in a converter array and digital synthesis filters to reconstruct the digitized signal. The HFB improves the speed and resolution of the conversion, in comparison to the standard time-interleaving technique by attenuating the effect of gain and phase mismatches between the ADCs. Many of the designs available in the literature are compromising between some metrics: design complexity, order of the filter bank (computation time) and the sharpness of the frequency response rolloff (the transition from the pass band to the stop band). In this dissertation, five different classes of near perfect magnitude reconstruction (NPMR) continuoustime hybrid filter banks (CT HFBs) are proposed. In each of the five cases, two filter banks are designed; analysis filter bank and synthesis filter bank. Since the systems are hybrid, continuous time IlR filter are used to implement the analysis filter bank and digital filters are used for the synthesis filter bank. To optimize the system, we used a new technique, known in the literature as frequency response masking (FRM), to design the synthesis filter bank. In this technique, the sharp roll-off characteristics can be achieved while keeping the complexity of the filter within practical range, this is done by splitting the filter into two filters in cascade; model filter with relaxed roll-off characteristics followed by a masking filter. One of the main factors controlling the overall complexity of the filter is the way of designing the model filter and that of designing the masking filter. The dissertation proposes three combinations: use of HR model filter and IlR masking filter, HR model filter/FIR masking filter and FIR model filter/FIR masking filter. To show the advantages of our designs, we considered the cases of designing the synthesis filter as one filter, either FIR or IlR. These two filters are used as base for comparison with our proposed designs (the use of masking response filter). The results showed the following: 1. Asymmetric hybrid filter banks alone are not sufficient for filters with sharp frequency response roll-off especially for HR/FIR class. 2. All classes that utilize FRM in their synthesis filter banks gave a good performance in general in comparison to conventional classes, such as the reduction of the order of filters 3. HR/HR FRM gave better performance than HR/FIR FRM. 4. Comparing HR/HR FRM using FIR masking filters and HR/IIR FRM using IIR masking filters, the latter gave better performance (the performance is generally measured in terms of reduced filter order). 5. All classes that use the FRM approach have a very low complexity, in terms of reduced filter order. Our target was to design a system with the following overall characteristics: pass band ripple of -0.01 dB, stop band minimum attenuation of - 40 dB and of response roll-off of 0.002. Our calculations showed that the order of the conventional IIR/FIR filter that achieves such characteristics is aboutN =2000. Using the FRM technique, the order N reduced to aboutN = 244, N = 179 for IIRJFIR and IIR/IIR classes, respectively. This shows that the technique is very effective in reducing the filter complexity. 6. The magnitude distortion and the aliasing noise are calculated for each design proposal and compared with the theoretical values. The comparisons show that all our proposals result in approximately perfect magnitude reconstruction (NPMR). In conclusion, our proposal of using frequency-response masking technique to design the synthesis filter bank can, to large extent, reduce the complexity of the system. The design of the system as a whole is simplified by designing the synthesis filter bank separately from the design of the analysis filter bank. In this case each bank is optimized separately. This implies that for SDR applications we are proposing the use of the continuous-time HFB ADC (CT HFB ADC) structure utilizing FRM for digital filters. / Thesis (M.Sc.Eng.)-University of KwaZulu-Natal, Durban, 2005.