Commercialization of infrared (IR) vision is of vital importance for many applications, such as automobile and health care. The main obstacle in front of the further spread of this technology is the high price. The cost reduction is achieved by placing on-chip electronics and diminishing the camera size, where one of the important components is the analog-to-digital converter (ADC). This thesis reports the design of a successive approximation register (SAR) ADC for low-cost microbolometers and its test electronics. Imaging ADCs are optimized only for the specific application in order to achieve the lowest power, yet the highest performance. The successive approximation architecture is chosen, due to its low-power, small-area nature, high resolution potential, and the achievable speed, as the ADC needs to support a 160x120 imager at a frame rate of 25 frames/sec (fps). The resolution of the ADC is 14 bit at a sampling rate of 700 Ksample/sec (Ksps). The noise level is at the order of 1.3 LSBs. The true resolution of the ADC is set to be higher than the need of the current low-cost microbolometers, so that it is not the limiting factor for the overall noise specifications. The design is made using a 0.18&micro / m CMOS process, for easy porting of design to the next generation low-cost microbolometers. An optional dual buffer approach is used for improved linearity, a modified, resistive digital-to-analog converter (DAC) is used for enhanced digital correction, and a highly configurable digital controller is designed for on-silicon modification of the device. Also, a secondary 16-bit high performance ADC with the same topology is designed in this thesis. The target of the high resolution ADC is low speed sensors, such as temperature sensors or very small array sizes of infrared sensors. Both of the SAR ADCs are designed without switched capacitor circuits, the operation speed can be minimized as low as DC if an extremely low power operation is required. A compact test setup is designed and implemented for the ADC. It consists of a custom designed proximity card, an FPGA card, and a PC. The proximity card is designed for high resolution ADC testing and includes all analog utilities such as voltage references, voltage regulators, digital buffers, high resolution DACs for reference generation, voltage buffers, and a very high resolution &Delta / -&Sigma / DAC for input voltage generation. The proximity card is fabricated and supports automated tests, because many components surrounding the ADC are digitally controllable. The FPGA card is selected as a commercially available card with USB control. The full chip functionalities and performances of both ADCs are simulated. The complete layouts of both versions are finished and submitted to the foundry. The ADC prototypes consist of more than 7500 transistors including the digital circuitry. The power dissipation of the 16-bit ADC is around 10mW, where the 14-bit device consumes 30mW. Each of the dies is 1mm x 5mm, whereas the active circuits occupy around 0.5mm x 1.5mm silicon area. These chips are the first steps in METU for the realization of the digital-in digital-out low cost microbolometers and low cost sensors.

The advent of deep submicron technology has resulted in a new generation of highly integrated mixed-signal system-on-chips (SoCs) and system-on-packages (SoPs). As a result, the cost of electrical products has sharply declined, and their performance has greatly improved. However, a testing throughput still remains one of the major contribution factors to final cost of the electrical products. In addition, highly precise and robust test methods and equipment are needed to promise non-defective products to customers. Hence, the testing is a critical part of the manufacturing process in the semiconductor industry. Testing such highly integrated systems and devices requires high-performance and high-cost equipment. Analog-to-digital converters (A/D converters) are the largest volume mixed-signal circuits, and they play a key role in communication between the analog and digital domains in many mixed-signal systems. Due to the increasing complexity of the mixed-signal systems and the availability of the new generations of highly integrated systems, reliable and robust data conversion schemes are necessary for many mixed-signal designs. Many applications such as telecommunications, instrumentation, sensing, and data acquisition have demanded data converters that support ultra high-speed, wide-bandwidths, and high-precision with excellent dynamic performance and low-noise. However, as resolutions and speeds in the A/D converters increase, testing becomes much harder and more expensive. In this research work, low-cost test strategies to reduce overall test cost for high-precision A/D converters are developed. The testing of data converters can be classified as dynamic (or alternating current (AC)) performance test and static (or direct current (DC)) performance test [1]. In the dynamic specification test, a low-cost test stimulus is generated using an optimization algorithm to stimulate high-precision sigma-delta A/D converters under test. Dynamic specifications are accurately predicted in two different ways using concepts of an alternate-based test and a signature-based test. For this test purpose, the output pulse stream of a sigma-delta modulator is made observable and useful. This technique does not require spectrally pure input signals, so the test cost can be reduced compared to a conventional test method. In addition, two low-cost test strategies for static specification testing of high-resolution A/D converters are developed using a polynomial-fitting method. The cost of testing can be significantly reduced as a result of the measurement of fewer samples than a conventional histogram test. While one test strategy needs no expensive high-precision stimulus generator, which can reduce the test cost, the other test strategy finds the optimal set of test-measurement points for the maximum fault coverage, which can use minimum-code measurement as a production test solution. The theoretical concepts of the proposed test strategies are developed in software simulation and validated by hardware experiments using a commercially available A/D converter and designed converters on printed circuit board (PCB). This thesis provides low-cost test solutions for the high-resolution A/D converters.

Typescript (photocopy). / Digitized by Kansas Correctional Industries

Typescript (photocopy). / Digitized by Kansas State University Libraries / Department: Electrical Engineering.

Call number: LD2668 .T4 1984 R428 / Master of Science

Call number: LD2668 .T4 1985 D63 / Master of Science

Call number: LD2668 .T4 1985 S246 / Master of Science

Power consumption is a critical issue for portable devices. The ever-increasing demand for multimode wireless applications and the growing concerns towards power-aware green technology make dynamically reconfigurable hardware an attractive solution for overcoming the power issue. This is due to its advantages of flexibility, reusability, and adaptability. During the last decade, reconfigurable analog-to-digital converters (ReADCs) have been used to support multimode wireless applications. With the ability to adaptively scale the power consumption according to different operation modes, reconfigurable devices utilise the power supply efficiently. This can prolong battery life and reduce unnecessary heat emission to the environment. However, current adaptive mechanisms for ReADCs rely upon external control signals generated using digital signal processors (DSPs) in the baseband. This thesis aims to provide a single-chip solution for real-time and low-power ReADC implementations that can adaptively change the converter resolution according to signal variations without the need of the baseband processing. Specifically, the thesis focuses on the analysis, design and implementation of a low-power digital controller unit for ReADCs. In this study, the following two important reconfigurability issues are investigated: i) the detection mechanism for an adaptive implementation, and ii) the measure of power and area overheads that are introduced by the adaptive control modules. This thesis outlines four main achievements to address these issues. The first achievement is the development of the switching activity measurement (SWAM) method to detect different signal components based upon the observation of the output of an ADC. The second achievement is a proposed adaptive algorithm for ReADCs to dynamically adjust the resolution depending upon the variations in the input signal. The third achievement is an ASIC implementation of the adaptive control module for ReADCs. The module achieves low reconfiguration overheads in terms of area and power compared with the main analog part of a ReADC. The fourth achievement is the development of a low-power noise detection module using a conventional ADC for signal improvement. Taken together, the findings from this study demonstrate the potential use of switching activity information of an ADC to adaptively control the circuits, and simultaneously expanding the functionality of the ADC in electronic systems.

Thesis (PhD)--University of Stellenbosch, 2004. / ENGLISH ABSTRACT: Analog-to-digital converters (ADCs) are an integral part of the interface between the analog and digital realms. This dissertation presents the design and simulation of a Complementary Output Switching-Logic (COSL) compatible, voltage state, switching logic comparator and a flash ADC for high speed applications with multi-GHz input bandwidth. Josephson technology and the COSL family of gates were utilized for this purpose. A detailed design for the switching logic comparator is first provided. The design is verified with simulations to obtain a functional comparator. The comparator is then optimized utilizing an optimization tool developed using the scripting facilities of WRSpice. Incorporated in this tool is a Monte Carlo capability to randomly vary the component values according to Gaussian distributions, and trimming facilities to be able to trim a non-functional comparator to restore functionality. The design component values are then optimized by maximizing the yield of a comparator. The optimized comparator is incorporated into the construction of a4-bit quantizer of an ADC. The output from the quantizer section yields a switching-logic Gray-code output. A Gray-to- Binary converter is designed with COSL gates to convert the Gray output from the quantizer into Binary code for further processing. The functionality, linearity, maximum input bandwidth and dynamic range of the 4-bit ADC is verified by simulation. A number of special input waveforms are used for this purpose. The performance of the comparator and the 4-bit ADC is also evaluated with thermal noise incorporated into simulation. Beat frequency simulations and Fourier spectra were also used in the evaluation of the ADC performance. A fully functional 4-bit ADC, with a maximum input bandwidth of 10 GHz for a clock speed of 20 GHz was achieved through simulations. Beat frequency simulations revealed that the comparators have an input bandwidth greater than 19 GHz with sufficient dynamic range for an ADC of greater than 6 bits of resolution. Due to the fact that the aperture time for the ADC is dependant on the rise time of the sampling pulse and not the width of the pulse, a much smaller aperture time is obtained which directly translates to higher input bandwidth. Finally, a layout of a 4-bit sampler circuit was done according to the Hypres manufacturing process to enable the high-speed testing of the comparator circuits. / AFRIKAANSE OPSOMMING: Analoog-na-Digitale Omsetters (ADOs) vorm 'n integrale deel van die koppelvlak tussen die analoog en digitale wêrelde. Hiedie proefskrif stel die ontwerp en simulasie van 'n Komplementêre Uittree Geskakelde Logika (COSL) aanpasbare, spanningstoestand, geskakelde logika vergelyker en ADO bekend. Hierdie ADO kan vir hoë spoed toepassings waar multi-GHz intree-bandwydte benodig word, aangewend word. Josephson tegnologie en die Komplementêre Uittree Geskakelde Logika (COSL) familie van hekke word vir hierdie doel gebruik. Die volledige ontwerp vir die geskakelde logika vergelyker word eerstens gegee. Die ontwerp word met behulp van simulasies bevestig om sodoende 'n ten volle funksionele vergelyker te verkry. Die vergelyker word verder geëptimeer deur middel van 'n proses wat met behulp van programmering in WRSpice ontwikkel is. Hierdie optimeringsproses sluit 'n Monte Carlo proses in wat die komponentwaardes van die vergelyker onwillekeurig volgens 'n Gaussiese verspreiding verander, sowel as 'n verstellingsmeganisme waarmee 'n nie-funksionerende vergelyker verstel kan word totdat dit weer ten volle funksioneer. Die komponentwaardes word dan geëptimeer vir maksimale opbrengs van 'n vergelyker. Die geëptimeerde vergelyker word gebruik in die konstruksie van 'n 4-bis kwantifiseerder vir 'n ADO. Die uittree van die 4-bis kwantifiseerder is in Gray kode. 'n Gray-na-Binêre kode omsetter word vir hierdie doelontwerp deur van COSL hekke gebruik te maak. Die volle ADO word voorts gesimuleer om die funksionalitet, lineariteit, maksimum intreebandwydte en dinamiese bereik te verifieer. 'n Verskeidenheid van intreeseine is vir hierdie doel gebruik. Die vergelyker en die 4-bis ADO is ook gesimuleer met termiese ruis om die effek daarvan te bepaal. Fourier spektra en ''verskilfrekwensie'' (Beat Frequency) simulasies word ook gebruik in die evaluering van die vergelyker en die ADO. Die korrekte werking van 'n 4-bis ADO met intreebandwydte van 10 GHz met 'n klokspoed van 20 GHz is deur simulasie bevestig. Verskilfrekwensie simulasies dui aan dat die vergelykers 'n intreebandwydte van groter as 19 GHz het, met voldoende dinamiese bereik vir 6 bis resolusie. Aangesien die vergelykers se venstertydperk bepaal word deur die stygende helling van die monsterpuls en nie deur die pulswydte nie, maak dit voorsiening vir 'n baie klein venstertydperk. 'n Klein venstertydperk is essensieel vir 'n hoë intreebandwydte. 'n Uitleg van 'n 4-bis vergelyker stadium is gedoen vir die Hypres vervaardigingsproses om die vergelyker teen hoë spoed te kan toets.

published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy