Continuous process scale-down and emerging markets for low-power/low-voltage mobile systems call for low-voltage analog integrated circuits. Switched-capacitor circuits are the building blocks for analog signal processing and will encounter severe overdrive problems when operating at low-voltage conditions. There are several well-known techniques to bypass the problem. These approaches include: (1) The clock boosting schemes (e.g. 2VDD clock signal) which cannot be used in submicron low-voltage CMOS processes as gate oxide can only tolerate the technology's maximum voltage (VDD). (2) The use of scaled/lower threshold transistors, which are not always scalable to very low voltage supplies as it could suffer from an unacceptable amount of leakage current (e.g. the switch may not be fully turned off). (3) The use of bootstrapped clocking, which has added loading and possible reliability issues. (4) The switched-opamp (SO) technique which is fully compatible with low-voltage submicron CMOS processes but the operating speed limited due to slow transients from the opamp being switched off and on. In this thesis, the Opamp-Reset Switching Technique (ORST) topology is proposed for low-voltage operation. Instead of opamps being turned on and off as in the switched-opamp technique, the sourcing amplifier is placed in the unity-gain reset configuration to provide reset level at the output. In this way, high-speed operation is possible. The technique is applied to two ADCs as examples of low-voltage design. The first design is a 10-bit 25MSPS pipelined ADC using pseudo-differential structure. It is fabricated in a 0.35-��m CMOS process. It operates at 1.4V and consumes 21mW of total power. The second design is a two-stage algorithmic ADC with highly linear input sampling circuit. In addition to the low-voltage design techniques used in the pipelined ADC, radix-based digital calibration technique for multi-stage ADC is also proposed. The ADC uses a 0.18-��m CMOS technology. It operates at 0.9V supply with total power consumption of 9mW. Experimental results show that the proposed calibration technique reduces spurious free dynamic range from 47dB to 75dB and improves signal-to-noise and distortion ratio from 40dB to 55dB after calibration. / Graduation date: 2003

Continuous process scale-down and emerging markets for low-power/low-voltage mobile systems call for low-voltage analog integrated circuits. Switched-capacitor (SC) circuits are the building blocks for analog signal processing and will encounter severe overdrive problems when operating at low voltage conditions. There exist three techniques to solve the problem, but with their own limitations. Multi-threshold process increases cost. Boosted clock will cause life time reliability issues. Switched-opamp slows down the speed of operation. A new low-voltage SC technique without special process and boosted-clock is studied to overcome these drawbacks. To verify the speed advantage of the new scheme over the switched-opamp technique, a 10-bit 20 MS/s pipeline A/D converter operating at 1.5 V supply voltage was designed. A new pseudo-differential structure was proposed and some relevant design issues are discussed. Circuit implementations and layout floorplan are described. All designs are based on Matlab, SWITCAP and Hspice simulation. / Graduation date: 2000

Multi-level decision feedback equalization (MDFE) is an effective sampled signal processing technique to remove inter-symbol interference (ISI) from disk read-back signals. Parallelism which doubles the symbol rate can be realized by utilizing the characteristic of channel response and decision feedback equalization algorithm. A mixed-signal IC implementation has been chosen for the parallel MDFE. The differential current signals from the feedback equalizer are subtracted from the forward equalizer output at the summing node to cancel the non-causal ISI. A high-speed comparator with 6 bit resolution is used after the cancellation to detect the signal which contains no ISI. In this thesis, a description of the parallel MDFE structure and decision feedback equalization algorithm are presented. The design of a high-speed summing circuitry and a high-speed comparator are discussed. The same comparator design is used for the flash analog-to-digital converter (ADC) which generates error signals for adaptation.The circuits design and layout were carried out in an HP 1.2-��m n-well CMOS process. / Graduation date: 1998

Graduation date: 1995

Oversampled analog-to-digital (A/D) converter architectures have been receiving increased attention for high-precision A/D converters. These architectures offer the means of exchanging resolution in time for that in amplitude. Among these oversampled A/D converters, delta-sigma modulators are the most popular method used due to their simplicity in the analog circuitry. The analog integrators in delta-sigma modulators suffer from non-idealities such as capacitor mismatches and finite op-amp gain. In the dual quantizer A/D converters, the system relies on the perfect matching of the analog and digital transfer functions to cancel the quantization noise. However, the non-ideality of the analog parameters makes this matching hard to achieve. In this thesis, an off-line adaptive scheme is presented to estimate the non-ideal parameters of the analog section for the second-order delta-sigma modulator. These estimates are then used in the digital part to reduce the quantization noise. The least-mean- square (LMS) algorithm is used to adaptively estimate the analog parameters. / Graduation date: 1993

Thesis (Ph. D.)--Oregon State University, 2007. / Printout. Includes bibliographical references (leaves 77-81). Also available on the World Wide Web.

Data converters, i.e., analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), are interface circuits between the analog and digital domains. They are used in, e.g., digital audio applications, data communication applications, and other types of applications where conversion between analog and digital signal representation is required. This work covers different aspects related to modeling, error correction, and implementation of DACs for communication applications where the requirements on the circuits in terms of speed and linearity are hard. The DAC architecture considered in this work is the current-steering DAC, which is the most commonly used architecture for high-speed applications. Transistor-level simulation of complex circuits using accurate transistor models require long simulation times. A transistor-level model of a DAC used in a system simulation is likely to be a severe bottleneck limiting the overall system simulation speed. Moreover, investigations of stochastic parameter variations require multiple simulation runs with different parameter values making transistor-level models unsuitable. Therefore, there is a need for behavioral-level models with reasonably short simulation times. Behavioral-level models can also be used to find the requirements on different building blocks on high abstraction levels, enabling the use of efficient topdown design methodologies. Models of different nonideal properties in current-steering DACs are used and developed in this work. Static errors typically dominates the low-frequency behavior of the DAC. One of the limiting factors for the static linearity of a current-steering DAC is mismatch between current sources. A well-known model of this problem is used extensively in this work for evaluation of different ideas and techniques for linearity enhancement. The highfrequency behavior of the DAC is typically dominated by dynamic errors. Models oftwo types of dynamic errors are developed in this work. These are the dynamic errors caused by parasitic capacitance in wires and transistors and glitches caused by asymmetry in the settling behavior of a current source. The encoding used for the digital control word in a current steering DAC has a large influence on the circuit performance, e.g., in terms static linearity and glitches. In this work, two DAC architectures are developed. These are denoted the decomposed and partially decomposed architectures and utilize encoding strategies aiming at a high circuit performance by avoiding unnecessary switching of current sources. The developed architectures are compared with the well-known binary-weighted and segmented architectures using behavioral-level simulations. It can be hard to meet a DAC design specification using a straightforward implementation. Techniques for compensation of errors that can be applied to improve the DAC linearity are studied. The well-known dynamic element matching (DEM) techniques are used for transforming spurious tones caused by matching errors into white or shaped noise. An overview of these techniques are given in this work and a DEM technique for the decomposed DAC architecture is developed. In DS modulation, feedback of the quantization error is utilized to spectrally shape the quantization noise to reduce its power within the signal band. A technique based on this principle is developed for spectral shaping of DAC nonlinearity errors utilizing a DAC model in a feedback loop. Two examples of utilization of the technique are given. Four different current-steering DACs implemented in CMOS technology are developed to enable comparison between behavioral-level simulations and measurements on actual implementations and to provide platforms for evaluation of different techniques for linearity improvement. For example, a 14-bit DEM DAC is implemented and measurement results are compared with simulation results. A good agreement between measured and simulated results is obtained. Moreover, a configurable 12-bit DAC capable of operating with different degrees of segmentation and decomposition is implemented to evaluate the proposed decomposed architecture. Measurement results agree with results from behavioral-level simulations and indicate that the decomposed architecture is a viable alternative to the commonly used segmented architecture.

The commercialization of Marconi’s radio transmission and reception, along with the development of integrated circuits in the 1960’s have facilitated many new consumer products for wireless communication, where the mobile phones or handsets are one. These handsets started out as a portable phone, mounted in cars, and have with time added additional services as Short Message Service, and have today become a media center with global positioning, and high-speed internet connection. This has been possible with the use of multistandard radios, that can receive and transmit information using many different wireless communication standards. Many of these handsets have one dedicated integrated radio chain for each communication standard used, which results in a large and expensive integrated circuit for these modern handsets. The challenge of today is to make modern handsets cheaper, smaller, and lower in power consumption. The power consumption is an issue of particular importance since the capacity of the available power sources do not increase with the demands of the handsets. One proposed method to do this is to move towards Software Defined Radio, where software of the handset control a single reconfigurable radio, and set which communication standard that the handset is to use. In this way, the handset can be reconfigured to communicate in the most power or data efficient way, depending on the choice of the user. The area of the Software Defined Radio receiver is also smaller than the parallel chains that are implemented today, which reduces the cost of production. The Software Defined Radio receiver is very challenging to design, since there is a large number of wireless communication standards, sometimes even within the same frequency bands. This make the reception of a weak desired signal difficult, when there may be a strong interferer in the same frequency band. A key component in the Software Defined Radio receiver is the Analog to Digital Converter. The development of new wireless communication standards requires higher performance of the Analog to Digital Converter in the receiver. This performance is hard to achieve, when the power consumption should be low, and the area should be small, especially in the modern integrated circuit technologies. This thesis put the development of the communication industry into a historical perspective, and gives a review of the fundamental development of wireless communication applications. The fundamental concepts and implementations of Analog to Digital Converters for multistandard wireless receiver chains are also covered. Finally two case studies on the design of multistandard Analog to Digital Converters for Software Defined Radio applications are presented. These Analog to Digital Converters implement different methods of reconfiguration in order to comply with the requirements of the standards. The first case study is to the knowledge of the author the first reported reconfigurable Analog to Digital Converter for Wireless Personal Area Networks, that can be reconfigured from Bluetooth to the UWB communication standard. This is done by changing the architecture of the Analog to Digital Converter from Sigma Delta type to flash type. This reconfigurable Analog to Digital Converter is implemented at transistor level. The second case study investigates the limits of circuit level reconfigurability in an algorithmic Analog to Digital Converter. It is found that the requirements of two wireless communication standards can be covered with the use of smart circuit design techniques. The performance of this Analog to Digital Converter has been validated with experimental measurements. / QC 20100729

This thesis presents two hybrid luminescence-based biochemical photosensory microsystems: a CMOS/microfluidic chemiluminescence contact imager, and a CMOS/thin-film fluorescence contact imager. A compact, low-power analog-to-digital converter (ADC) architecture for use in such sensory microsystems is also proposed. Both microsystems are prototyped in a standard 0.35um CMOS technology. The CMOS/microfluidic microsystem integrates a 64x128-pixel CMOS imager and a soft polymer microfluidic network. Circuit techniques are employed to reduce the dark current and circuit noise for low-level light sensitivity. Experimental validation is performed by detecting luminol chemiluminescence and electrochemiluminescence. The CMOS/thin-film microsystem integrates an existing 128x128-pixel CMOS imager and a prefabricated, high-performance optical filter. Experimental validation is performed by detecting human DNA labeled with Cyanine-3 fluorescent dye. The proposed ADC architecture employs a novel digital-to-analog converter with a flexible trade-off between the integration area and the conversion speed. The area savings and good linearity of the DAC are verified by simulations.

Most present day implementations of delta-sigma modulators are discrete-time ones using switched-capacitor circuits. A resistor-capacitor (RC) implementation of a delta-sigma analog to digital converter (ADC) does not use switched capacitor (SC) technology. While SC implementation has the advantages of being discrete-time, no resistors used and improved stability control, RC implementation has the advantage of no switches being used (other than quantizer) and therefore a simpler circuit implementation. Continuous-time implementations can achieve lower thermal noise levels than switched capacitor modulators. Butterworth Multi-stage Noise Shaping (MASH) architecture is one of the promising architectures to implement in continuous-time domain. For a convenient design and quantization noise spectrum shaping of a delta sigma data converter, it's highly desirable for the Noise Transfer Function (NTF) to take the form of a high-pass filter. The MASH architecture was introduced to overcome stability problems commonly faced beyond a second order structure. Delta-sigma data converters are new converter designs that are preferred for integrated circuits and for high-resolution applications. It is highly desirable for the NTF of delta-sigma data converters to take the form of conventional highpass filters for convenient design purposes and shaping of the quantization noise spectrum. However, conventional delta-sigma architectures allow for only low orders and very low cutoff frequencies for such highpass filters, otherwise the converter becomes unstable. In previous projects it was found that a MASH implementation (each stage being second order) of a delta-sigma data converter where the NTF of each stage is a Butterworth highpass filter holds much promise. This current project is to accomplish RC implementation of fourth-order Butterworth MASH delta-sigma data converter. The circuit design procedure will be shown, starting with the desired NTF characteristics, and yielding the required parameters for the RC integrators with gains that are determined from the desired transfer function. The circuit simulation, yielding the bit stream frequency spectrum and the signal to noise ratio, will be based on Mentor Graphics Eldo SPICE simulations. The performance and characteristics of the circuit is fully analyzed and documented for a wide variety of variations and test conditions. / Thesis (M.S.)--Wichita State University, College of Engineering, Dept. of Electrical and Computer Engineering. / "August 2006." / Includes bibliographic references (leaves 41-43).