This work is the result of the definition, design and evaluation of a novel method to interconnect the computational elements - commonly known as Configurable Analogue Blocks (CABs) - of a programmable analogue array. This method is proposed for total or partial replacement of the conventional methods due to serious limitations of the latter in terms of scalability. With this method, named Asynchronous Spike Event Coding (ASEC) scheme, analogue signals from CABs outputs are encoded as time instants (spike events) dependent upon those signals activity and are transmitted asynchronously by employing the Address Event Representation (AER) protocol. Power dissipation is dependent upon input signal activity and no spike events are generated when the input signal is constant. On-line, programmable computation is intrinsic to ASEC scheme and is performed without additional hardware. The ability of the communication scheme to perform computation enhances the computation power of the programmable analogue array. The design methodology and a CMOS implementation of the scheme are presented together with test results from prototype integrated circuits (ICs).

Abstract This thesis describes the development of low-voltage, low-power circuit blocks and structures for portable, battery-operated applications such as heart rate detectors, pacemakers and hearing-aid devices. In this work, the definition for low supply voltage operation is a voltage equal to or less than the minimum supply voltage needed to operate an analogue switch, i.e. VDD(min) ≤ 2VT + Vov, which enables the use of a single cell battery whose polar voltage is 1 – 1.5 V. The targeted power consumption is in a range of microwatts. The design restrictions for analogue circuit design caused by the low supply voltage requirement of the latest and future CMOS process technologies were considered and a few circuit blocks, namely two operational amplifiers, a Gm–C filter and a bandgap voltage reference circuit, were first designed to investigate their feasibility for the above-mentioned low-voltage and low-power environment. Two operational amplifiers with the same target specifications were designed with two different types of input stages, i.e. a floating-gate and a bulk-driven input stage, in order to compare their properties. Based on the experiences collected from the designed circuit blocks, an analogue CMOS preprocessing stage for a heart rate detector and a self-calibrating RC oscillator for clock and resistive/capacitive sensor applications were designed, manufactured and tested. The analogue preprocessing stage for a heart rate detector includes a continuous-time offset-compensated preamplifier with a gain of 40 dB, an 8th-order switched-opamp switched-capacitor bandpass filter, a 32-kHz crystal oscillator and a bias circuit, and it achieves the required performance with a supply voltage range of 1.0 – 1.8 V and a current consumption of 3 μA. The self-calibrating RC oscillator operates with supply voltages of 1.2 – 3.0 V and achieves a tunable frequency range of 0.2 – 150 MHz with a total accuracy of ±1% within a supply voltage range of 1.2 – 1.5 V, a temperature range from -20 to 60 °C and a current consumption of less than 70 μA @ 5 MHz with external high precision resistor and capacitor. The measurement results prove that the developed low-voltage low-power analogue circuit structures can achieve the required performance and therefore be successfully implemented with modern CMOS process technologies with limited supply voltages. / Tiivistelmä Tämä väitöskirja käsittelee matalan käyttöjännitteen pienitehoisten piirirakenteiden kehittämistä kannettaviin, paristokäyttöisiin sovelluksiin kuten esimerkiksi sykemittareihin, sydämen tahdistimiin ja kuulolaitteisiin. Matalalla käyttöjännitteellä tarkoitetaan jännitettä, joka on pienempi tai yhtäsuuri kuin analogisen kytkimen tarvitsema pienin mahdollinen käyttöjännite, VDD(min) ≤ 2VT + Vov, joka mahdollistaa piirin toiminnan yhdellä paristolla, jonka napajännite on 1 – 1,5 V. Tavoiteltu tehonkulutus on mikrowattiluokkaa. Piirirakenteiden suunnittelussa otettiin huomioon viimeisimpien ja lähitulevaisuuden CMOS-valmistusteknologioiden aiheuttamat matalan käyttöjännitteen erityisvaatimukset ja niiden pohjalta kehitettiin aluksi kaksi erilaista operaatiovahvistinta, GmC-suodatin, ja bandgap-jännitereferenssi. Operaatiovahvistimet toteutettiin samoin tavoitevaatimuksin kahdella eri tekniikalla käyttäen toisen vahvistimen tuloasteessa ns. kelluvahilaisia tulotransistoreita ja toisen tuloasteessa ns. allasohjattuja tulotransistoreita. Kehitetyistä rakenteista saatujen kokemusten pohjalta suunniteltiin, valmistettiin ja testattiin kaksi erilaista CMOS-teknologialla toteutettua mikropiiriä, jotka olivat analoginen esikäsittelypiiri sydämen sykkeen mittaukseen ja itsekalibroiva RC-oskillaattori resistiivisiin/kapasitiivisiin sensorisovelluksiin. Sydämen sykkeen esikäsittelypiiri sisältää jatkuva-aikaisen, offset-kompensoidun esivahvistimen, jonka vahvistus on 40 dB, kytketyistä kapasitansseista ja kytketyistä operaatiovahvistimista koostuvan kahdeksannen asteen kaistanpäästösuodattimen, 32 kHz kideoskillaattorin ja bias-piirin. Esikäsittelypiiri saavuttaa vaadittavan suorituskyvyn 1,0 – 1,8 V käyttöjännitteellä ja 3 μA virrankulutuksella. Itsekalibroivan RC-oskillaattorin käyttöjännitealue puolestaan on 1,2 – 3,0 V ja käyttökelpoinen taajuusalue 0,2 – 150 MHz. Ulkoista tarkkuusvastusta ja kondensaattoria käytettäessä oskillaattori saavuttaa ±1 % tarkkuuden 1,2 – 1,5 V käyttöjännitteillä ja -20 – 60 °C lämpötila-alueella virrankulutuksen jäädessä alle 70 μA @ 5 MHz. Mittaustulokset osoittavat, että kehitetyt matalan käyttöjännitteen pienitehoiset analogiset rakenteet saavuttavat vaadittavan suorituskyvyn ja voidaan näin ollen menestyksekkäästi valmistaa moderneilla matalan käyttöjännitteen CMOS-teknologioilla.

This work presents an analogue baseband (BB) chain for a magnetic tunneling junction (MTJ) based radiofrequency (RF) signal detector fully integrated in a hybrid CMOS-MTJ technology. The BB chain contains a 6 th -order gm-C low-pass filter (LPF), a BB amplifier, a comparator, and a current bank. According to measurement results, the 6 th -order LPF with a cut-off frequency of 10 MHz consumes a very low DC power of 2.41 mW. Its DC power consumption per pole of 0.4 mW is the lowest among the state-of-the-art LPFs. The LPF can be also switched on and off very fast within 110 ns. With the fast switch-ability and the low power consumption, the LPF outperforms the state of the art. Furthermore, the complete BB chain can transform a 2.5 Vpp, 5 Mbps BB signal into digital data with a bit error rate fewer than 1e−6 . The BB chain consumes 2.85mW including all bias circuits. To achieve power efficiency, the BB chain is designed to operate under an aggressive duty-cycling mode. The switch-on time of the BB chain is within 200 ns

This master thesis presents an analogue peak holder circuit design aimed at facilitating the non-invasive inspection of the ageing process in electric drives. The ageing process of electric drives is a crucial aspect that demands accurate monitoring to ensure their long-term performance and reliability. The proposed peak holder circuit is specifically designed to detect fast and narrow-width pulses of ringing current present in the PWM drive current. By capturing and measuring the peak values of these pulses, the circuit provides valuable insights into the ageing characteristics of electric drives. Experimental results demonstrate the remarkable efficiency of the peak holder circuit in accurately detecting and quantifying the peak values of the ringing current pulses. The circuit exhibits a stable output swing within a specified effective input swing range, with low mean-squared error (MSE) values. This signifies a strong linear correlation between the input and output signals, enhancing the reliability of the ageing detection process. The ability of the peak holder circuit to effectively detect and analyze the ageing process of electric drives offers numerous advantages. By focusing on peak detection, which captures the highest values of the ringing current, the circuit provides a more efficient and targeted approach to inspecting the ageing process. This enables engineers and maintenance personnel to gain crucial insights into the degradation and performance of electric drives, allowing for timely interventions and proactive maintenance. / Detta examensarbete presenterar en nyutvecklad kretslösning för toppvärdesdetektering hos elektriska drivsystem, med målet att underlätta ickeinvasiv övervakning av åldrandesprocessen hos eldrivsystem. Åldrandet hos eldrivsystem är en avgörande faktor som kräver noggrann övervakning för att säkerställa deras långsiktiga prestanda och tillförlitlighet. Den föreslagna kretsen för att detektera toppvärden är specifikt utformad för att detektera snabba och kortvariga ringningar i PWM-modulerade strömmar. Genom att mäta toppvärdena ger kretsen värdefull information om åldrandekaraktären hos eldrivsystemen. Experimentella resultat visar på den enastående effektiviteten hos spetsdetekteringskretsen för att noggrant detektera och kvantifiera toppvärdena hos ringningarna i strömmen. Kretsen uppvisar en stabil utsignal inom ett specificerat ingångsintervall, med låga medelkvadratiska felvärden (MSE). Detta indikerar en stark linjär korrelation mellan ingångs- och utgångssignalerna, vilket förbättrar tillförlitligheten hos åldersdetektionsprocessen. Krestsens förmåga att effektivt detektera och analysera åldrandeprocessen hos eldrivsystem erbjuder flera fördelar. Genom att fokusera på toppvärdesdetektering, som fångar de högsta värdena av ringströmmen, ger kretsen ett mer effektivt och riktat tillvägagångssätt för att inspektera åldrandet. Det möjliggör för ingenjörer och underhållspersonal att få viktig information om nedbrytning och prestanda hos eldrivsystem, vilket möjliggör tidiga insatser och proaktivt underhåll.

The aim of this work was to create a system for optimisaton of specific analog circuits by evolution using multiple fitness functions . A set of experiments was run, and the results analyzed to evaluate the feasibility of evolutionary optimisation of analog circuits . A requirement for this goal is the study and choice of certain types of analog circuits and evolutionary algorithms . For the scope of this work , amplifiers and oscillators were chosen as target circuits , and genetic algorithms and evolutionary strategies as evolutionary algorithms . The motivation for this work is the ongoing effort to automate the design and optimisation of analog circuits , where evolutionary optimisation is one of the options .