Packaged microelectronic technology provides an efficient means to connecting high performance chips to PCBs. As area array bump density increases, joule heating will play an important role in chip and interconnect reliability. Joule heating, in addition to chip heating can significantly reduce the clock speed and I/O while increasing noise, electromigration, and leakage power. Direct cooling of the solder bumps is a new innovative approach to removing heat from packaged high heat dissipating chips. This could be used in conjunction with top surface mounted thermal management devices to maximize heat removal. The solder bumps leave a small gap between the packaged chip and PCB, which can be utilized for incorporating a thermal management scheme. Since space is very limited, fans and conventional heat sinks are not practical solutions. Jet impingement presents a unique solution for cooling solder bumps. It has been shown that micro jets can effectively cool the top surface of laptop computer processors. They can also be used to cool the solder bumps and bottom of the chip. Micro jets are easily implemented into the PCB without compromising the electrical leads powering the chip. A prototype printed wiring board containing micro jets was built and a dummy plastic ball grid array packaged chip with a heating element embedded in it was attached on top. A mini compressor supplied the pressure and flow rates needed to push air through the micro jet holes. The pressure, flow rate, and temperatures were measured and analyzed. A numerical model was created based on the results of the experiments. Both the experiments and model show the effectiveness of interconnect cooling.

Recently, consumer electronics industry has known a spectacular growth that would have not been possible without pushing the integration barrier further and further. Micro Electro Mechanical Systems (MEMS) inertial sensors (e.g. accelerometers, gyroscopes) provide high performance, low power, low die cost solutions and are, nowadays, embedded in most consumer applications. In addition, the sensors fusion has become a new trend and combo sensors are gaining growing popularity since the co-integration of a three-axis MEMS accelerometer and a three-axis MEMS gyroscope provides complete navigation information. The resulting device is an Inertial measurement unit (IMU) able to sense multiple Degrees of Freedom (DoF). Nevertheless, the performances of the accelerometers and the gyroscopes are conditioned by the MEMS cavity pressure: the accelerometer is usually a damped system functioning under an atmospheric pressure while the gyroscope is a highly resonant system. Thus, to conceive a combo sensor, aunique low cavity pressure is required. The integration of both transducers within the same low pressure cavity necessitates a method to control and reduce the ringing phenomena by increasing the damping factor of the MEMS accelerometer. Consequently, the aim of the thesis is the design of an analog front-end interface able to sense and control an underdamped three-axis MEMSaccelerometer. This work proposes a novel closed-loop accelerometer interface achieving low power consumption The design challenge consists in finding a trade-off between the sampling frequency, the settling time and the circuit complexity since the sensor excitation plates are multiplexed between the measurement and the damping phases. In this context, a patenteddamping sequence (simultaneous damping) has been conceived to improve the damping efficiency over the state of the art approach performances (successive damping). To investigate the feasibility of the novel electrostatic damping control architecture, several mathematical models have been developed and the settling time method is used to assess the damping efficiency. Moreover, a new method that uses the multirate signal processing theory and allows the system stability study has been developed. This very method is used to conclude on the loop stability for a certain sampling frequency and loop gain value. Next, a 0.18μm CMOS implementation of the entire accelerometer signal chain is designed and validated.

La simulation numérique d'écoulements complexes telles que les turbulences ou la propagation d'ondes de choc implique un temps de calcul conséquent pour une précision industrielle acceptable. Pour accélérer ces simulations, deux recours peuvent être combinés : l'adaptation de maillages afin de réduire le nombre de points d'une part, et le parallélisme pour absorber la charge de calcul d'autre part. Néanmoins réaliser un portage efficient des noyaux adaptatifs sur des architectures massivement parallèles n'est pas triviale. Non seulement chaque tâche relative à un voisinage local du domaine doit être propagée, mais le fait de traiter une tâche peut générer d'autres tâches potentiellement conflictuelles. De plus, les tâches en question sont caractérisées par une faible intensité arithmétique ainsi qu'une faible réutilisation de données déjà accédées. Par ailleurs, l'avènement de nouveaux types de processeurs dans le paysage du calcul haute performance implique un certain nombre de contraintes algorithmiques. Dans un contexte de réduction de la consommation électrique, ils sont caractérisés par de multiples cores faiblement cadencés et une hiérarchie mémoire profonde impliquant un coût élevé et asymétrique des accès-mémoire. Ainsi maintenir un rendement optimal des cores implique d'exposer un parallélisme très fin et élevé d'une part, ainsi qu'un fort taux de réutilisation de données en cache d'autre part. Ainsi la vraie question est de savoir comment structurer ces noyaux data-driven et data-intensive de manière à respecter ces contraintes ?Dans ce travail, nous proposons une approche qui concilie les contraintes de localité et de convergence en termes d'erreur et qualité de mailles. Plus qu'une parallélisation, elle s'appuie une re-conception des noyaux guidée par les contraintes hardware en préservant leur précision. Plus précisément, nous proposons des noyaux locality-aware pour l'adaptation anisotrope de variétés différentielles triangulées, ainsi qu'une parallélisation lock-free et massivement multithread de noyaux irréguliers. Bien que complémentaires, ces deux axes proviennent de thèmes de recherche distinctes mêlant informatique et mathématiques appliquées. Ici, nous visons à montrer que nos stratégies proposées sont au niveau de l'état de l'art pour ces deux axes. / Numerical simulations of complex flows such as turbulence or shockwave propagation often require a huge computational time to achieve an industrial accuracy level. To speedup these simulations, two alternatives may be combined : mesh adaptation to reduce the number of required points on one hand, and parallel processing to absorb the computation workload on the other hand. However efficiently porting adaptive kernels on massively parallel architectures is far from being trivial. Indeed each task related to a local vicintiy need to be propagated, and it may induce new conflictual tasks though. Furthermore, these tasks are characterized by a low arithmetic intensity and a low reuse rate of already cached data. Besides, new kind of accelerators have arised in high performance computing landscape, involving a number of algorithmic constraints. In a context of electrical power consumption reduction, they are characterized by numerous underclocked cores and a deep hierarchy memory involving asymmetric expensive memory accesses. Therefore, kernels must expose a high degree of concurrency and high cached-data reuse rate to maintain an optimal core efficiency. The real issue is how to structure these data-driven and data-intensive kernels to match these constraints ?In this work, we provide an approach which conciliates both locality constraints and convergence in terms of mesh error and quality. More than a parallelization, it relies on redesign of kernels guided by hardware constraints while preserving accuracy. In fact, we devise a set of locality-aware kernels for anisotropic adaptation of triangulated differential manifold, as well as a lock-free and massively multithread parallelization of irregular kernels. Although being complementary, those axes come from distinct research themes mixing informatics and applied mathematics. Here, we aim to show that our devised schemes are as efficient as the state-of-the-art for both axes.

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