No description available.

No description available.

Ultra narrow-band filters and the use of two loops in a cascade configuration dominate current clock conditioners based on phase-locked-loop (PLL) schemes. Since a PLL exhibits a low-pass transfer function with respect to the reference clock, the noise performance at very close-to-carrier offset frequencies is still determined by the input signal. Although better cleaning can be achieved with extremely narrow loops, an ultra low cut-off frequency could not be selected since the stability of the configuration deteriorates as the filter bandwidth is reduced. This fact suggests that a full-spectrum clock conditioning is not possible using traditional PLL architectures, and an alternative scheme is necessary to attenuate the very-close-to-carrier phase noise (PN). In addition, ultra-narrow loop filters can compromise on-chip integration because of the large size capacitors needed when chosen as passive. Input signal attenuation with relaxed bandwidth requirements becomes the main aspect that a comprehensive clock cleaner must address to effectively regenerate a reference signal. This dissertation describes the Band-Reject Nested-PLL (BRN-PLL) scheme, a modified PLL-based architecture that provides an effective signal cleaning procedure by introducing a notch in the input transfer function through inner and outer loops and a high-pass filter (HPF). This modified response attenuates the reference-signal PN and reduces the size of the loop-filter capacitors substantially. Ultra narrow loops are no longer required because the notch size is related to the system bandwidth. The associated transfer function for the constitutive blocks (phase detectors and local oscillators) show that the output close-to-carrier and far-from-carrier PN sections are mainly dominated by the noise from the inner-PLL phase detector (PD) and local oscillator (LO) located in the outer loop, respectively. The inner-PLL PD transfer function maintains a low-pass characteristic with a passband gain inversely proportional to the PD gain becoming the main contribution around the carrier signal. On the other hand, the PN around the transition frequency is determined mainly by the reference and the inner-PLL LO. Their noise contributions to the output will depend on the associated passband local maxima, which is located at the BRN-PLL transition frequency. Hence, in this region, the inner-PLL LO is selected so that its effect can be held below that of the outer-PLL PD. The BRN-PLL can use a high-Q MEMS-based VCO to further improve the transition region of the output PN profile and an LC-VCO as outer-PLL LO to reduce the noise floor of the output signal. In particular, two tuning mechanisms are explored for the MEMS-VCO: series tuning using varactors and phase shifting of a resonator operating in nonlinear regime. Both schemes are implemented to generate a tunable oscillator with no PN-performance degradation.

Le but de ce travail était de développer des filtres passe-bande RF dans la technologie de PCB, avec trois objectifs principaux. Le premier objectif était de développer des formules de synthèse tosimplify la procédure de conception du filtre. Le deuxième était de parvenir à un rejet wideout bande sans modifier les caractéristiques de la bande de filtrage. Le troisième objectif est de contrôler la fréquence centrale du filtre en utilisant diode varicap. / The purpose of this work was to develop RF bandpass filters in PCB technology,with three main objectives. The first objective was to develop synthesis formulas tosimplify the design procedure of the filter. The second was to achieve wideout-of-band rejection without modifying the in-band filtering characteristics. Thethird objective was to control the center frequency of the filter by using varactordiode.The bandpass filter topology treated in this thesis is based on Stub-LoadedResonators (SLR). The main features of this filter topology were treated. Equivalentcircuits based on J-inverters and susceptance parameters were derived. Based onthese equivalent circuits, synthesis formulas were developed. Simulations werepresented to validate the synthesis theory. For a proof-of-concept, third orderstripline bandpass filters were designed and fabricated based on this synthesis.Analysis technique using odd- and even- mode was achieved on the SLR. Thusresonance odd- and even-mode conditions were derived. These conditions aim toeasily control the first spurious frequency. Moreover, to go further in improving theout-of-band rejection a new technique, called “U corner structure”, was developedand design rules were derived. Based on these design rules an extended out-of-bandrejection was achieved without any modification in the passband and by maintainingthe compactness of the filter. A first spurious frequency was localized at up to ninetimes the working frequency in the case of the Parallel-coupled Stub-Loadedresonator (PC-SLR) filter. Also, by applying this technique into the classicalparallel-coupled filter the first and second spurious frequencies were rejected. Toaddress the issue of tunable filters, the SLRs were correctly loaded by variablecapacitors (varactor diode). The center frequency of the PC-SLR filter was easilycontrolled by maintaining a large out-of-band rejection.