Software Defined Radios (SDRs) and Cognitive Radios (CRs) pave the way for next-generation radio technology. They promise versatility, flexibility and cognition which can revolutionize communications systems. However they present greater challenges to the design of radio frequency (RF) front-ends. RF front-ends for the radios in use today are narrow-band in their frequency response and are optimized and tuned to the carrier frequency of interest. SDRs and CRs demand front-ends which are versatile, configurable, tunable and be capable of transmitting and receiving signals with different bandwidths and modulation schemes. Integrating power amplifiers (PAs) with transmitters in CMOS has many advantages and challenges. This thesis deals with the design of an RF transmitter front-end for SDRs and CRs in CMOS. The thesis begins with an introduction to SDRs and the requirements they place on transmitters and the challenges involved in designing them in CMOS. After a brief overview of the existing techniques, the proposed architecture is presented and explained. A digitally intensive transmitter solution is proposed. The transmitter covers a wide frequency range of 750 MHz to 2.5 GHz. The inputs to the proposed transmitter are in-phase and quadrature (I & Q) data bit streams. Multiple stages of up-sampling and filtering are used to remove all spurs in the spectrum such that only the harmonics of the carrier remain. Differential rail-to-rail quadrature clocks are generated from a continuous wave signal at twice the carrier frequency. The clocks are corrected for their duty cycle and quadrature impairments. The heart of the transmitter is an integrated reconfigurable CMOS power amplifier (PA). A methodology to design reconfigurable Class E PAs with a series fixed inductor has been presented. A CMOS power amplifier that can span a wide frequency range with sufficient output power and efficiency, supporting varying envelope complex modulation signals, with good linearity has been designed. Digital pre-distortion (DPD) is used to linearize the PA. The full transmitter and the clock correction blocks have been designed and fabricated in a commercial 130-nm CMOS process and experimentally characterized. The PA delivers a maximum power of 13 dBm with an efficiency of 27% at 1 GHz. While transmitting a 16-QAM signal at 1 GHz, the measured EVM is 4%. It delivers a maximum power of around 11-13 dBm from 750 MHz to 1.5 GHz and up to 6.5 dBm of power till 2.5 GHz. Comparing the proposed system with recently published literature, it can be seen that the proposed design is one of the very few transmitters which has an integrated matching network, tunable across the frequency range. The proposed PA produces the highest output power and with largest efficiency for systems with on-chip output networks.

Afin de répondre à la demande croissante du nombre d'objets connectés et de débits de données plus élevés, la cinquième génération de réseau mobile (5G) va être déployée.Pour répondre à ces défis, la 5G utilisera le beamforming pour améliorer la qualité de transmission et étendre la couverture du réseau. En raison du manque de spectre RF disponible en dessous de 6 GHz, l'industrie de la téléphonie mobile étudie actuellement les bandes de fréquences millimétriques en particulier autour de 28 GHz. L'utilisation de la technologie CMOS pour les applications 5G apparait prometteuse pour le marché de masse que vise la 5G, d'autant qu'aujourd'hui la miniaturisation des transistors CMOS permet un fonctionnement compétitif aux fréquences millimétriques. Pour répondre à toutes les attentes de la 5G notamment en termes de fiabilité, de nouvelles idées en rupture, avec le self-healing et le self-contained, permettent d’utiliser au maximum les avantages de la technologie CMOS tout en proposant un fonctionnement fiable pou rl’amplificateur. Dans le cadre du self-healing et du self-contained, plusieurs circuits son tintégrés sur silicium tel qu'un amplificateur intégrant un détecteur de puissance totalement non invasif pour le self-healing et un amplificateur équilibré pour le selfcontained. / In order to meet the growing demand for more connected objects and higher data rates,the fifth generation of mobile network (5G) will be deployed. To address thesechallenges, the 5G will use beamforming to improve the transmission quality and extendthe network coverage. Due to the lack of available RF spectrum below 6 GHz, the mobileindustry is studying millimeter wave frequency bands in particular around 28 GHz. Theuse of CMOS technology for 5G applications is promising for the 5G mass market,especially nowadays the miniaturization of CMOS transistors allows competitiveoperation at millimeter frequencies. To meet all the expectations of the 5G especially interms of reliability, new breakthrough ideas, with the self-healing and the selfcontained,allow to use all the benefits of CMOS technology to the maximum whileoffering reliable operation for the amplifier. Within the framework of self-healing andself-contained, several circuits are integrated on silicon such as an amplifier integratedwith a totally non-invasive power detector for self-healing and a balanced self-containedamplifier.

Dans le cadre des applications sans fil à 60GHz, l’amplificateur de puissance reste un des composants les plus compliqués à implémenter en technologie CMOS. Des modulations à enveloppe non constante obligent à concevoir des circuits hautement linéaires, conduisant à une consommation statique importante. La recherche de topologies et de techniques de linéarisation viables aux fréquences millimétriques fait l’objet de cette thèse. Dans un premier temps, un état de l’art des différents amplificateurs de puissance à 60GHz est dressé, afin d’en extraire l’ensemble des verrous technologiques limitant leurs performances. Suite à l’analyse des phénomènes physiques impactant les composants passifs, plusieurs structures d’amplificateurs élémentaires sont conçues dans les technologies 65nm et 28nm Bulk. Les topologies les plus pertinentes sont déduites de cette étude. Enfin, deux amplificateurs intégrant des techniques de combinaison de puissance et de linéarisation sont implémentés dans les technologies 65nm et 28nm FD-SOI. Ces deux circuits présentent les plus hauts facteurs de mérite ITRS publiés à ce jour. Le circuit en 28nm FD-SOI atteint en outre le meilleur compromis linéarité/consommation de l’état de l’art. / The CMOS 60GHz power amplifier (PA) remains one of the most design-challenging components. Indeed, a high linearity associated with a large back-off range are required due to complex modulated signals.In this context, this work focuses on the design of architectures and linearization techniques which are usable at millimeter-wave frequencies. First, a CMOS PA state of the art is presented to define all bottlenecks. Then, the physical phenomena impacting on passive device performances are described. Elementary PAs are implemented in CMOS 65nm and 28nm Bulk and the most suitable topologies are selected. Finally, two highly linear circuits are designed in 65nm Bulk and 28nm FD-SOI. They achieve the highest ITRS figures of merit reported to this day. In addition, the 28nm FD-SOI PA exhibits the best linearity/consumption tradeoff.