Cell-based design is a widely adopted design approach in current Application Specific Integrated Circuits (ASIC) and System-on-Chip (SOC) designs. A standard cell library is a collection of basic building blocks that can be used in cell-based design. The use of a standard cell library offers shorter design time, induces fewer errors in the design process, and is easier to maintain. Development of a cell library is laborious, prone to errors and even a small error on a library cell can possibly be disastrous due to repeated use of the cell in a design. In this thesis, we investigated ways to automate the process for development of a cell library, specifically TSMC 0.18-micron CMOS standard cell library. We examined various steps in the design flow to identify required repetitive tasks for individual cells. Those steps include physical verification, netlist extraction, cell characterization, and generation of Synopsys Liberty Format file. We developed necessary scripts in Skill, Tcl, Perl and Shell to automate those steps. Additionally, we developed scripts to automate the quality assurance process of the cell library, where quality assurance consists of verifying the entire ASIC design flow adopted for the Virginia Tech VLSI Telecommunications (VTVT) lab. Our scripts have been successfully used to develop our TSMC 0.18-micron library and to verify the quality assurance. The first version of the cell library was released on November 1, 2007 to universities worldwide, and as of March 2008, 20 universities have received the library from us. / Master of Science

This thesis focuses on the design and implementation of low power Σ∆ ADCs in 130 nanometer CMOS technology. The design issues in the implementation of a third order ADC with a multi-bit and single bit quantizer are discussed. The advancement in CMOS technology has led to designing as much of electronics systems as possible with the digital circuits and digital signal processing replacing analog processing in most cases. Hence there is a need for digitizing analog signals with analog to digital converter (ADC). In communication systems this needs to be done immediately after the antenna in a receiver system. As this is difficult to implement due to high speed and high power consumption, RF signal is converted to a lower intermediate frequency (IF) and digitized. This work stresses low power implementation of high bandwidth Σ∆ ADCs for digitizing the IF. Design techniques involved in the implementation of a third order continuous time Σ∆ ADC with a 4 bit quantizer as well as a single bit quantizer for wide bandwidth are discussed. Moreover, a third order continuous time audio ADC implementation was also done. The behavioural modelling of the Σ∆ ADC along with clock jitter non-linearity model was developed and the issues in circuit design techniques are addressed. The continuous time ADCs’ major problem, namely, excess loop delay is discussed in detail and an efficient compensation technique for the same is implemented which allows a large reduction of power consumed by the ADC. Choice of loop filter architecture, quantizer and transistor level implementation are given that result in better immunity to offsets and process variations. Both the ADCs have been implemented using UMC 130 nm Mixed-mode RF-CMOS process and the simulation results for the multi-bit ADC gives a peak SNR of 56dB with a dynamic range of 65dB with power consumption of 2mW. The audio ADC achieves a peak SNR of 94.2dB with a dynamic range of 91dB.

L’objectif de ce travail est de concevoir et de caractériser un front-end millimétriqueutilisant des lignes de propagation à ondes lentes S-CPW optimisées en technologies CMOS avancées.Ces lignes présentant des facteurs de qualité 2 à 3 fois supérieurs à ceux des lignes classiques de typemicroruban ou CPW.Dans le premier chapitre, l’impact de l’évolution des noeuds technologiques CMOS sur lesperformances des transistors MOS aux fréquences millimétriques et sur les lignes de propagation ainsiqu’un état de l’art concernant les performances des front-end sont présentés. Le deuxième chapitreconcerne la réalisation des lignes S-CPW dans différentes technologies CMOS et la validation d’unmodèle phénoménologique électrique équivalent. Le troisième chapitre est dédié à la conceptiond’amplificateurs de puissance à 60 GHz utilisant ces lignes S-CPW en technologies CMOS 45 et65 nm. Cette étude a permis de mettre en évidence l’apport des lignes à ondes lentes aux performancesdes amplificateurs de puissance fonctionnant dans la gamme des fréquences millimétriques. Uneméthode de conception basée sur les règles d’électro-migration et permettant une optimisation desperformances a été développée. Finalement, un amplificateur faible bruit et un commutateur d’antennetravaillant à 60 GHz et à base de lignes S-CPW ont été conçus en technologie CMOS 65 nm afin degénéraliser l’impact de ce type de lignes sur les performances des front-end millimétriques. / The objective of this work is to design and characterize a millimeter-wave front-end usingthe optimized slow-wave transmission lines S-CPW in advanced CMOS technologies. The qualityfactor of these transmission lines is twice to three times higher than that of the conventionaltransmission lines such as microstrip lines and coplanar waveguides.In the first chapter, the influence of CMOS scaling-down on the performance of transistors atmillimeter-wave frequencies and on the transmission lines was studied. In addition, a state of the artwith regard to the performance of the front-end was presented. The second chapter concerns about therealization of the S-CPW lines in different CMOS technologies and the validation of an electricalequivalent model. The third chapter is dedicated to the design of 60-GHz power amplifiers using theseS-CPW lines in CMOS 45 and 65 nm technologies. This study highlighted the performanceenhancement of power amplifiers operating at millimeter-wave frequencies by using the slow-wavetransmission lines. A design method based on the electro-migration rules was also developed. Finally,a low noise amplifier and an antenna switch operating at 60 GHz were designed in CMOS 65 nm inorder to generalize the impact of such transmission lines on the performance of the millimeter-wavefront-end.