Thesis (M.S.)--University of Wisconsin--Madison. / Typescript. eContent provider-neutral record in process. Description based on print version record. Includes bibliographical references (leaves 96-100).

Thesis (Ph. D.)--University of Washington, 2002. / Vita. Includes bibliographical references (p. 126-131).

Stuttgart, Univ., Diplomarb., 2004.

Thesis (M.S.) B.Y.U. Dept. of Religion.

Thesis (Ph. D.)--Brigham Young University. Dept. of Computer Science, 2005. / Includes bibliographical references (p. 363-374).

Thesis (M.S.)--Oregon State University, 2006. / Printout. Includes bibliographical references (leaves 19-20). Also available on the World Wide Web.

Thesis (Ph. D.)--University of Texas at Austin, 2006. / Vita. Includes bibliographical references.

Thesis (M.Comp. Sc.)--Dept. of Computer Science, Concordia University, 1997. / "April 1997." Includes bibliographical references (leaves 74-77). Available also on the Internet.

Thesis (Ph.D.)--University of Texas at Dallas, 2007. / Includes vita. Includes bibliographical references (leaves 199-209)

Directly mapped caches are an attractive option for processor designers as they combine fast lookup times with reduced complexity and area. However, directly-mapped caches are prone to higher miss-rates as there are no candidates for replacement on a cache miss, hence data residing in a cache set would have to be evicted to the next level cache. Another issue that inhibits cache performance is the non-uniformity of accesses exhibited by most applications: some sets are under-utilized while others receive the majority of accesses. This implies that increasing the size of caches may not lead to proportionally improved cache hit rates. Several solutions that address cache non-uniformity have been proposed in the literature. These techniques have been proposed over the past decade and each proposal independently claims the benefit of reduced conflict misses. However, because the published results use different benchmarks and different experimental setups, (there is no established frame of reference for comparing these results) it is not easy to compare them. In this work we report a side-by-side comparison of these techniques. Finally, we propose and Adaptive-Partitioned cache for multi-threaded applications. This design limits inter-thread thrashing while dynamically reducing traffic to heavily accessed sets.